MoBL
®
Clock
M4000/M8000
Four-PLL Programmable Clock Generator
for Portable Applications
Four-PLL Programmable Clock Generator for Portable Applications
Features
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Benefits
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Device Operating Voltage Options:
❐
MoBL Clock M4000 Family: 1.8 V
❐
MoBL Clock M8000 Family: 2.5 V, 3.0 V, or 3.3 V
Selectable clock output voltages for both MoBL Clock M4000
and M8000:
❐
1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V
Fully integrated ultra low power phase-locked loops (PLLs)
Input reference clock frequency range:
❐
External crystal: 8 to 48 MHz
❐
External reference: 1 to 48 MHz clock
Output clock frequency range: 3–50 MHz
Up to eight I
2
C™ programmable output clocks
Programmable output drive strengths
150 ps typical cycle-to-cycle jitter
Optional Spread Spectrum for EMI reduction
24-pin (4 × 4 × 1 mm) QFN Package
Industrial temperature range
Suitable for cell phone, portable, and consumer electronics
applications
Replaces multiple crystals or crystal oscillators enabling board
space saving
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Capable of Zero PPM frequency synthesis error
Application compatibility in multiple output voltage levels
Optional Spread Spectrum capable PLLs with Lexmark or
Linear profile for maximum EMI reduction
Programmable PLLs for system frequency margin tests
Meets critical timing requirements in complex system designs
Individually enable or disable each output using I
2
C
Ease of output clock selection using programmable crossbar
switches
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Logic Block Diagram
CLK1
XIN/
EXCLKIN
XOUT
OSC
PLL1
Crossbar
Switch
Output
Dividers
and
Drive
Bank
2
Bank
1
CLK2
CLK3
CLK4
CLK5
CLK6
Bank
3
MUX
and
Control
SCL
SDA
I2C
Logic
PLL2
Strength
Control
CLK7
CLK8
PLL3
(SS)
PLL4
(SS)
SSON
PD # / OE
Cypress Semiconductor Corporation
Document Number: 001-29179 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 7, 2010
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MoBL
®
Clock
M4000/M8000
Contents
Pinouts .............................................................................. 3
MoBL Clock M4000 ..................................................... 3
MoBL Clock M8000 ..................................................... 4
General Description ......................................................... 5
4 Configurable PLLs .................................................... 5
I2C Programming ........................................................ 5
Input Reference Clocks ............................................... 5
Output Power Supply Options ..................................... 5
Output Source Selection ............................................. 5
Spread Spectrum Control ............................................ 5
PD#/OE Mode ............................................................. 5
Keep Alive Mode ......................................................... 5
Output Drive Strength .................................................. 5
Factory Specific Configuration and
Custom Programming ......................................................... 5
I2C Serial Interface ........................................................... 6
Device Address ........................................................... 6
Data Valid .................................................................... 6
Data Frame ................................................................. 6
Acknowledge Pulse ..................................................... 6
Write Operations ............................................................... 6
Writing Individual Bytes ............................................... 6
Writing Multiple Bytes .................................................. 6
Read Operations ............................................................... 6
Current Address Read ................................................. 6
Random Read ............................................................. 6
Sequential Read .......................................................... 6
Serial Programming Interface Timing ............................. 8
Serial I2C Programming Interface
Timing Specifications ...................................................... 8
Absolute Maximum Conditions ....................................... 9
Recommended Operating Conditions ............................ 9
DC Electrical Specifications .......................................... 10
AC Electrical Specifications .......................................... 11
Recommended Crystal Specification for
SMD Package .................................................................. 11
Test and Measurement Setup ........................................ 12
Voltage and Timing Definitions ..................................... 12
Recommended Crystal Specification for
Thru-Hole Package ......................................................... 12
Ordering Information ...................................................... 13
Possible Configurations ............................................. 13
Ordering Code Definitions ......................................... 13
Package Drawing and Dimensions ............................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Document Number: 001-29179 Rev. *C
Page 2 of 17
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MoBL
®
Clock
M4000/M8000
Pinouts
MoBL Clock M4000
Figure 1. Pin Diagram - 24LD QFN
XIN/
EXCLKIN
XOUT
CLK8
20
24
23
22
21
GND
CLK1
VDD_CLK_B1
PD#/OE
VDD
CLK2
GND
19
DNU
VDD
1
18
GND
CLK7
VDD_CLK_B3
CLK6/SSON
VDD_CLK_B2
CLK5
2
17
3
MoBL Clock M4000
24 LD QFN
16
4
15
5
14
6
13
7
8
9
10
11
12
CLK3
SCL
CLK4
GND
Table 1. Pin Definitions - MoBL Clock M4000 Family (VDD = 1.8 V Supply)
Pin Number
1
Name
GND
IO
Power
Power Supply Ground
GND
SDA
Description
Programmable Clock Output,
Output voltage depends on
VDD_CLK_B1
voltage
Power Supply for Bank1 (CLK1, CLK2) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLK1
VDD_CLK_B1
PD#/OE
VDD
CLK2
GND
SCL
SDA
CLK3
CLK4
GND
CLK5
VDD_CLK_B2
CLK6/SSON
VDD_CLK_B3
CLK7
GND
GND
CLK8
DNU
VDD
XOUT
XIN/EXCLKIN
Output
Power
Input
Power
Output
Power
Input
Input/Output
Output
Output
Power
Output
Power
Output/Input
Power
Output
Power
Power
Output
Input
Power
Output
Input
Multifunction Programmable pin: Output Enable or Power Down Modes
Power Supply: 1.8 V
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B1
voltage
Power Supply Ground
Serial Data Clock
Serial Data Input/Output
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B2
voltage
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B2
voltage
Power Supply Ground
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B2
voltage
Power Supply for Bank2 (CLK3, CLK4, CLK5) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Multifunction Programmable pin: Programmable Clock Output or
Spread Spectrum
control input pin. Output voltage depends on
VDD_CLK_B3
voltage
Power Supply for Bank3 (CLK6, CLK7, CLK8) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B3
voltage
Power Supply Ground
Power Supply Ground
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B3
voltage
Do Not Use
Power Supply: 1.8 V
Crystal Output
Crystal Input or 1.8 V External Reference Clock Input
Document Number: 001-29179 Rev. *C
Page 3 of 17
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MoBL
®
Clock
M4000/M8000
MoBL Clock M8000
Figure 2. Pin Diagram - 24LD QFN
XIN/
EXCLKIN
XOUT
CLK8
20
24
23
22
21
GND
19
DNU
VDD
GND
CLK1
VDD_CLK_B1
PD#/OE
DNU
CLK2
1
18
GND
CLK7
VDD_CLK_B3
CLK6/SSON
VDD_CLK_B2
CLK5
2
17
3
MoBL Clock M8000
24LD QFN
16
4
15
5
14
6
13
7
8
9
10
11
12
CLK3
Table 2. Pin Definitions - MoBL Clock M8000 Family (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
1
Name
GND
Power
IO
Power Supply Ground
CLK4
SDA
GND
GND
SCL
Description
Programmable Clock Output,
Output voltage depends on
VDD_CLK_B1
voltage
Power Supply for Bank1 (CLK1, CLK2) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CLK1
PD#/OE
DNU
CLK2
GND
SCL
SDA
CLK3
CLK4
GND
CLK5
CLK6/SSON
Output
Input
DNU
Output
Power
Input
Input/Output
Output
Output
Power
Output
Output/Input
VDD_CLK_B1 Power
Multifunction Programmable pin: Output Enable or Power Down Modes
Do Not Use
Programmable Clock Output,
Output voltage depends on
VDD_CLK_B1
voltage
Power Supply Ground
Serial Data Clock
Serial Data Input/Output
Programmable Clock Output,
Output voltage depends on
VDD_CLK_B2
voltage
Programmable Clock Output,
Output voltage depends on
VDD_CLK_B2
voltage
Power Supply Ground
Programmable Clock Output,
Output voltage depends on
VDD_CLK_B2
voltage
Power Supply for Bank2 (CLK4, CLK4, CLK5) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Multifunction Programmable pin: Programmable Clock Output or
Spread Spectrum
ON/OFF control input pin. Output voltage depends on
VDD_CLK_B3
voltage
Power Supply for Bank3 (CLK6, CLK7, CLK8) outputs: 1.5 V/1.8 V/2.5 V/3.0 V/3.3 V
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B3
voltage
Power Supply Ground
Power Supply Ground
Programmable Clock Output.
Output voltage depends on
VDD_CLK_B3
voltage
Do Not Use
VDD_CLK_B2 Power
VDD_CLK_B3 Power
CLK7
GND
GND
CLK8
DNU
VDD
XOUT
Output
Power
Power
Output
Input
Power
Output
Power Supply: 2.5 V/3.0 V/3.3 V
Crystal Output
XIN/EXCLKIN Input
Crystal Input or
1.8 V
External Reference Clock Input
Document Number: 001-29179 Rev. *C
Page 4 of 17
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MoBL
®
Clock
M4000/M8000
General Description
4 Configurable PLLs
The MoBL
®
Clock M4000/M8000 family of products are four-PLL
Clock Generator ICs designed for cell phone, portable, or
consumer electronics applications. It can be used to generate
four independent output frequencies ranging from 3 to 50 MHz
from a single input reference clock.
range from –0.25% to –5.0%, with Lexmark or Linear modulation
profile.
PD#/OE Mode
PD#/OE input (Pin 4) can be programmed to operate as either
power down (PD#) or output enable (OE) mode. Note that power
down shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings. The
PD# turn-on time is limited by the turn-on time of the PLLs.
Disabled outputs are first driven to a low state before turning off.
When off, they are held low by internal weak resistors
(~160 k ohms)
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
I
2
C Programming
The MoBL
®
Clock, M4000 and M8000 have a serial I
2
C interface
that programs the configuration memory array to synthesize
output frequencies by programmable output divider, spread
characteristics, and drive strength. I
2
C can also be used for
in-system control of these programmable features.
Input Reference Clocks
The input to the M4000 and M8000 can be either a crystal or a
clock signal. The input frequency range for crystals is 8 MHz to
48 MHz, while that for EXCLKIN is 1 to 48 MHz. The voltage level
for the input reference clock used must meet the voltage
requirement for the device as shown in the DC and AC
specifications.
Keep Alive Mode
By activating the device in the Keep Alive Mode, power down
mode is changed to power saving mode, which disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Thus, any configuration changes made via the I
2
C interface are
preserved. By deactivating the Keep Alive Mode, I
2
C memory is
not preserved during power down, but power consumption is
reduced relative to the Keep Alive Mode.
Output Power Supply Options
These devices have eight clock outputs grouped in three banks.
The Bank 1, Bank 2, and Bank 3 correspond to (CLK1, CLK2),
(CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8) respectively. A
separate power supply is used for each of these three output
drivers and they can be any of 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V
giving user multiple choice of output clock voltage levels.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values.
Table 3
shows the typical rise
and fall times for different drive strength settings.
Table 3. Output Drive Strength
Output Drive Strength
Low
Mid Low
Mid High
High
Rise/Fall Time (ns)
(Typical Value)
6.8
3.4
2.0
1.0
Output Source Selection
These devices have eight clock outputs (CLK1–8). There are five
available clock sources for these outputs. These clock sources
are: XIN/EXCLKIN, PLL1, PLL2, PLL3 and PLL4. Output clock
source selection is done using four out of five crossbar switch.
Thus, any one of these five available clock sources can be
arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock and a reference
clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off by I
2
C
device programming. It can be factory programmed to either
center spread range from ±0.125% to ±2.50%, or down spread
Factory Specific Configuration and Custom
Programming
The device is available with Factory Specific programmed
frequencies as shown in the Ordering Information page. This
factory specific programmed part can be used for the device
evaluation purposes. The MoBL
®
Clock can be custom
programmed to any desired frequencies and listed features. For
customer specific programming and I
2
C programmable memory
bitmap definitions, please contact local Cypress Field Appli-
cation Engineer (FAE) or sales representative.
Document Number: 001-29179 Rev. *C
Page 5 of 17
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