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M40SZ100Y

M40SZ100W

5V or 3V NVRAM SUPERVISOR FOR LPSRAM

FEATURES SUMMARY

CONVERT LOW POWER SRAMs INTO

NVRAMs

Figure 1. 16-pin SOIC Package

5V OR 3V OPERATING VOLTAGE

PRECISION POWER MONITORING and

POWER SWITCHING CIRCUITRY

AUTOMATIC WRITE-PROTECTION WHEN

IS OUT-OF-TOLERANCE

CHOICE OF SUPPLY VOLTAGES and

POWER-FAIL DESELECT VOLTAGES:

– M40SZ100Y: V

= 4.5 to 5.5V;

4.20V

≤

PFD

≤

4.50V

– M40SZ100W: V

= 2.7 to 3.6V;

2.55V

≤

PFD

≤

2.70V

RESET OUTPUT (RST) FOR POWER ON

RESET

1.25V REFERENCE (for PFI/PFO)

LESS THAN 10ns CHIP ENABLE ACCESS

PROPAGATION DELAY (at 5V)

OPTIONAL PACKAGING INCLUDES A 28-

LEAD SOIC and SNAPHAT

TOP (to be

ordered separately)

28-LEAD SOIC PACKAGE PROVIDES

DIRECT CONNECTION FOR A SNAPHAT

TOP WHICH CONTAINS THE BATTERY

BATTERY LOW PIN (BL)

Figure 2. 28-pin SOIC Package*

SNAPHAT (SH)

Battery

SO16 (MQ)

SOH28 (MH)

* Contact Local Sales Office

September 2003

Rev. 1.3

1/19

M40SZ100Y, M40SZ100W

TABLE OF CONTENTS

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Logic Diagram (Figure 3.) . . . . . . .

Signal Names (Table 1.) . . . . . . . .

SOIC16 Connections (Figure 4.) . .

SOIC28 Connections (Figure 5.) . .

Block Diagram (Figure 6.) . . . . . . .

Hardware Hookup (Figure 7.) . . . .

.......

......

.......

......

.......

......

...........3

...........4

...........5

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Ratings (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC and AC Measurement Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AC Testing Load Circuit (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AC Testing Input/Output Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Capacitance (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC Characteristics (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Data Retention Lifetime Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Down Timing (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power Up Timing (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power Down/Up AC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Power-on Reset Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset Input (RSTIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RSTIN Timing Waveform (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset AC Characteristics (Table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Battery Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-fail Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Supply Voltage Protection (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

SNAPHAT® Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/19

M40SZ100Y, M40SZ100W

SUMMARY DESCRIPTION

The M40SZ100Y/W NVRAM Controller is a self-

contained device which converts a standard low-

power SRAM into a non-volatile memory. A preci-

sion voltage reference and comparator monitors

the V

input for an out-of-tolerance condition.

When an invalid V

condition occurs, the condi-

tioned chip enable output (E

CON

) is forced inactive

to write protect the stored data in the SRAM. Dur-

ing a power failure, the SRAM is switched from the

pin to the lithium cell within the SNAPHAT (or

external battery for the 16-lead SOIC) to provide

the energy required for data retention. On a sub-

sequent power-up, the SRAM remains write pro-

tected until a valid power condition returns.

The 28-pin, 330 mil SOIC provides sockets with

gold plated contacts for direct connection to a sep-

arate SNAPHAT

housing containing the battery.

The SNAPHAT housing has gold plated pins

which mate with the sockets, ensuring reliable

connection. The housing is keyed to prevent im-

proper insertion. This unique design allows the

SNAPHAT battery package to be mounted on top

of the SOIC package after the completion of the

surface mount process which greatly reduces the

board manufacturing process complexity of either

directly soldering or inserting a battery into a sol-

dered holder. Providing non-volatility becomes a

“SNAP.” This feature is also available in the “top-

less” 16-pin SOIC package (MQ).

Insertion of the SNAPHAT housing after reflow

prevents potential battery damage due to the high

temperatures required for device surface-mount-

ing. The SNAPHAT housing is also keyed to pre-

vent reverse insertion.

The 28-pin SOIC and battery packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form. For the 28-lead SOIC, the bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber is “M4ZXX-BR00SH” (see Table 13, page 17).

Caution:

Do not place the SNAPHAT battery top

in conductive foam, as this will drain the lithium

button-cell battery.

Figure 3. Logic Diagram

VCC VBAT

(1)

Table 1. Signal Names

CON

RST

Chip Enable Input

Conditioned Chip Enable Output

Reset Output (Open Drain)

Reset Input

Battery Low Output (Open Drain)

Supply Voltage Output

Supply Voltage

Back-up Supply Voltage

Power Fail Input

Power Fail Output

Ground

Not Connected Internally

VOUT

PFI

RSTIN

M40SZ100Y

M40SZ100W

RSTIN

OUT

ECON

PFO

BAT (1)

RST

PFI

PFO

VSS

Note: 1. For 16-pin SOIC package only.

AI03933

Note: 1. For SO16 only.

3/19

M40SZ100Y, M40SZ100W

Figure 4. SOIC16 Connections

Figure 5. SOIC28 Connections

RST

RSTIN

PFO

VBAT

VSS

4 M40SZ100Y 13

5 M40SZ100W 12

VCC

VOUT

PFI

ECON

AI03935

RSTIN

PFO

VSS

7 M40SZ100Y 22

8 M40SZ100W 21

AI03934

VCC

VOUT

PFI

RST

ECON

Note: 1. DU = Do Not Use

Figure 6. Block Diagram

VCC

VOUT

VBAT

VBL= 2.5V

COMPARE

(1)

VSO = 2.5V

COMPARE

VPFD= 4.4V

COMPARE

POR

(2.65V for SZ100W)

RSTIN

RST(1)

PFI

COMPARE

1.25V

ECON

PFO

AI04766

Note: Open drain output

4/19

M40SZ100Y, M40SZ100W

Figure 7. Hardware Hookup

3.0V, 3.3V or 5V

Regulator

Unregulated

Voltage

VIN

VCC

VOUT

VCC

M40SZ100Y

M40SZ100W

From Microprocessor

RSTIN

PFI

VSS

VBAT

(1)

RST

To Microprocessor Reset

To Battery Monitor Circuit

ECON

PFO

To Microprocessor NMI

0.1µF

1Mb or 4Mb

LPSRAM

0.1µF

AI04767

Note: 1. User supplied for the 16-pin package

MAXIMUM RATING

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

Table 2. Absolute Maximum Ratings

Symbol

STG

SLD(1)

Parameter

Storage Temperature (V

Off)

Lead Solder Temperature for 10 seconds

Input or Output Voltages

Supply Voltage

Output Current

Power Dissipation

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Value

SNAPHAT

SOIC

–40 to 85

–55 to 125

260

–0.3 to V

+0.3

M40SZ100Y

M40SZ100W

–0.3 to 7

–0.3 to 4.6

Unit

°C

Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120

seconds).

CAUTION:

Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

CAUTION:

Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

5/19