SODIMM
DDR2 SDRAM
DDR2 Unbuffered SODIMM
200pin Unbuffered SODIMM based on 1Gb R-die
64-bit Non-ECC
60FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 17
Rev. 1.2 July 2008
SODIMM
Table of Contents
DDR2 SDRAM
1.0 DDR2 Unbuffered SODIMM Ordering Information .................................................................... 4
2.0 Features ........................................................................................................................................ 4
3.0 Address Configuration ................................................................................................................ 4
4.0 Pin Configurations (Front side/Back side) ................................................................................ 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Input/Output Function Description ............................................................................................ 6
7.0 Functional Block Diagram : ........................................................................................................ 7
7.1 2GB, 256Mx64 Module - M470T5663RZ3
......................................................................................... 7
7.2 1GB, 128Mx64 Module - M470T2863RZ3
......................................................................................... 8
8.0 Absolute Maximum DC Ratings ................................................................................................. 9
9.0 AC & DC Operating Conditions .................................................................................................. 9
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
...................................................................... 9
9.2 Operating Temperature Condition
............................................................................................... 10
................................................................................................................. 10
9.4 Input AC Logic Level
................................................................................................................. 10
9.5 AC Input Test Conditions
........................................................................................................... 10
10.0 IDD Specification Parameters Definition ................................................................................11
11.0 Operating Current Table .......................................................................................................... 12
11.1 M470T5663RZ3 : 2GB(128Mx8 *16) Module
.................................................................................. 12
11.2 M470T2863RZ3 : 1GB(128Mx8 *8) Module
................................................................................... 12
12.0 Input/Output Capacitance ....................................................................................................... 13
13.0 Electrical Characteristics & AC Timing for DDR2-800/667 .................................................. 13
13.1 Refresh Parameters by Device Density
....................................................................................... 13
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
............................................ 13
13.3 Timing Parameters by Speed Grade
........................................................................................... 14
14.0 Physical Dimensions : ............................................................................................................ 16
14.1 128Mbx8 based 256Mx64 Module (2 Rank) - M470T5663RZ3
.......................................................... 16
14.2 128Mbx8 based 128Mx64 Module (1 Rank) - M470T2863RZ3
.......................................................... 17
9.3 Input DC Logic Level
2 of 17
Rev. 1.2 July 2008
SODIMM
Revision History
Revision
1.0
1.1
1.2
Month
March
April
July
Year
2008
2008
2008
- Initial Release
- Added new product
- Applied JEDEC update(JESD79-2E) on AC timing table
History
DDR2 SDRAM
3 of 17
Rev. 1.2 July 2008
SODIMM
1.0 DDR2 Unbuffered SODIMM Ordering Information
Part Number
M470T5663RZ3-CF7/E6
M470T2863RZ3-CF7/E6
Density
2GB
1GB
Organization
256Mx64
128Mx64
Component Composition
128Mx8(K4T1G084QR-HCF7/E6)*16
128Mx8(K4T1G084QR-HCF7/E6)*8
DDR2 SDRAM
Number of Rank Height
2
1
30mm
30mm
Note :
1. “Z” of Part number(12th digit) stand for Lead-free products.
2. “H” of Part number(12th digit) stand for Lead-free, Halogen-free and RoHS compliant products.
3. “3” of Part number(13th digit) stand for Dummy Pad PCB products.
2.0 Features
• Performance range
F7 (DDR2-800)
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
-
533
667
800
6-6-6
E6 (DDR2-667)
400
533
667
-
5-5-5
Unit
Mbps
Mbps
Mbps
Mbps
CK
• JEDEC standard 1.8V ± 0.1V Power Supply
• V
DDQ
= 1.8V ± 0.1V
• 333MHz f
CK
for 667Mb/sec/pin, 400MHz f
CK
for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T
CASE
85°C, 3.9us at 85°C < T
CASE
< 95
°C
-
support High Temperature Self-Refresh rate enable feature
• Package: 60ball FBGA - 128Mx8
• All of base components are Lead-free, Halogen-free and RoHS compliant
Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
128Mx8(1Gb) based Module
Row Address
A0-A13
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10
4 of 17
Rev. 1.2 July 2008
SODIMM
4.0 Pin Configurations (Front side/Back side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1
DQS1
V
SS
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
Pin
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Front
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
A8
V
DD
A5
A3
Pin
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Back
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3
DQS3
V
SS
DQ30
DQ31
V
SS
NC/CKE1
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
Pin
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Front
A1
V
DD
A10/AP
BA0
WE
V
DD
CAS
NC/S1
VDD
NC/ODT1
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
A0
V
DD
BA1
RAS
S0
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5
DQS5
V
SS
Pin
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DDR2 SDRAM
Front
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC, TEST
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DD
SPD
Pin
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
CK1
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.
5.0 Pin Description
Pin Name
CK0,CK1
CK0,CK1
CKE0,CKE1
RAS
CAS
WE
S0,S1
A0~A9, A11~A13
A10/AP
BA0~BA2
ODT0,ODT1
SCL
CK0,CK1
Description
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
SDRAM Bank Address
On-die termination control
Serial Presence Detect(SPD) Clock Input
Clock Inputs, positive line
Pin Name
SDA
SA1,SA0
DQ0~DQ63
DM0~DM7
DQS0~DQS7
DQS0~DQS7
TEST
V
DD
V
SS
V
REF
V
DD
SPD
NC
SDA
SPD address
Data Input/Output
Data Masks
Data strobes
Data strobes complement
Logic Analyzer specific test pin
(No connect on So-DIMM)
Core and I/O Power
Ground
Input/Output Reference
SPD Power
Spare pins, No connect
SPD Data Input/Output
Description
SPD Data Input/Output
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
5 of 17
Rev. 1.2 July 2008
