M48T212A
3.3V TIMEKEEPER
®
CONTROLLER
PRELIMINARY DATA
s
CONVERTS LOW POWER SRAM into
NVRAMs
YEAR 2000 COMPLIANT (4-Digit Year)
USES SUPER CAPACITOR or LITHIUM
BATTERY (User Supplied)
BATTERY LOW FLAG
INTEGRATED REAL TIME CLOCK,
POWER-FAIL CONTROL CIRCUIT
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WATCHDOG TIMER
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48T212A: 2.7V
≤
V
PFD
≤
3.0V
MICROPROCESSOR POWER-ON RESET
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP MODE
4
A0-A3
A
E
EX
W
G
WDI
RSTIN1
RSTIN2
X0
XI
M48T212A
IRQ/FT
RST
E1CON
E2CON
VCCSW
VOUT
s
s
s
s
44
1
SOH44 (MH)
s
s
s
s
s
Figure 1. Logic Diagram
VCC
VCAP
DESCRIPTION
The M48T212A is a self-contained device that in-
cludes a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
A built-in 32.768 kHz oscillator (external crystal
controlled) is used for the clock/calendar function.
Access to all TIMEKEEPER functions and the ex-
ternal RAM is the same as conventional byte-wide
SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Control, Calibration, Alarm, Watchdog,
and Flags. Externally attached static RAMs are
controlled by the M48T212A via the E1
CON
and
E2
CON
signals (see Table 4).
Automatic backup and write protection for an ex-
ternal SRAM is provided through V
OUT
, E1
CON
and E2
CON
pins. (Users are urged to insure that
voltage specifications, for both the controller chip
and external SRAM chosen, are similar).
8
DQ0-DQ7
VSS
VBAT–
AI03047
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/20
M48T212A
Figure 2. SOIC Connections
Table 1. Signal Names
A0-A3
DQ0-DQ7
XO
Address Inputs
Data Inputs/Outputs
Oscillator Output
Oscillator Input
Reset 1 Input
Reset 2 Input
Reset Output (Open Drain)
Watchdog Input
Bank Select Input
Chip Enable Input
External Chip Enable Input
Output Enable Input
Write Enable Input
RAM Chip Enable 1 Output
RAM Chip Enable 2 Output
Int/Freq Test Output (Open Drain)
V
CC
Switch Output
Supply Voltage Output
Super Capacitor Input
Battery Ground Pin (optional)
Supply Voltage
Ground
Not Connected internally
RSTIN1
RSTIN2
RST
NC
XO
XI
NC
NC
A
NC
NC
NC
A3
A2
A1
A0
WDI
E2CON
DQ0
DQ1
DQ2
VSS
44
1
43
2
3
42
4
41
40
5
39
6
38
7
37
8
36
9
35
10
34
11
M48T212A
33
12
32
13
31
14
30
15
29
16
28
17
27
18
26
19
25
20
24
21
23
22
AI03048
VCC
VOUT
VCCSW
IRQ/FT
EX
NC
NC
NC
NC
NC
G
W
VBAT–
NC
E
E1CON
DQ7
DQ6
DQ5
DQ4
DQ3
VCAP
XI
RSTIN1
RSTIN2
RST
WDI
A
E
EX
G
W
E1
CON
E2
CON
IRQ/FT
Vccsw
V
OUT
V
CAP
V
BAT–
V
CC
V
SS
NC
The lithium energy source (or super capacitor)
used to permanently power the real time clock is
also used to retain RAM data in the absence of
V
CC
power through the V
OUT
pin.
The chip enable outputs to RAM (E1
CON
and
E2
CON
) are controlled during power transients to
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years. The internal watchdog tim-
er provides programmable alarm windows.
The nine clock bytes (Fh - 9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT
TM
read/write memory cells
within the static RAM array. Clock circuitry up-
dates the clock bytes with current information once
per second. The information can be accessed by
the user in the same manner as any other location
in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
2/20
tains the watchdog timer setting. The watchdog
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
bit (WDS). Bytes 6h-2h include bits that, when pro-
grammed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
The M48T212A also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the TIMEKEEPER register data and
external SRAM, providing data security in the
midst of unpredictable system operation. As V
CC
falls, the control circuitry automatically switches to
the battery, maintaining data and clock operation
until valid power is restored.
M48T212A
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
SLD (2)
V
IO
V
CC
I
O
P
D
Parameter
Ambient Operating Temperature
Storage Temperature (V
CC
Off, Oscillator Off)
Lead Solder Temperature for 10 sec
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
Value
0 to 70
–55 to 125
260
–0.3 to 4.6
–0.3 to 4.6
20
1
Unit
°C
°C
°C
V
V
mA
W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
(1)
Mode
Deselect
Write
3.0V to 3.6V
Read
Read
Deselect
Deselect
V
SO
to V
PFD
(min)
(2)
≤
V
SO (2)
V
IL
V
IL
X
X
V
IL
V
IH
X
X
V
IH
V
IH
X
X
D
OUT
High-Z
High-Z
High-Z
Active
Active
CMOS Standby
Battery Back-Up
V
CC
E
V
IH
V
IL
G
X
X
W
X
V
IL
DQ7-DQ0
High-Z
D
IN
Power
Standby
Active
Note: 1. X = V
IH
or V
IL
.
2. V
SO
= Battery Back-up Switchover Voltage. (See Table 7 for details).
Table 4. Truth Table for SRAM Bank Select
(1)
Mode
Select
3.0V to 3.6V
Deselect
Deselect
Deselect
V
SO
to V
PFD
(min)
(2)
≤
V
SO (2)
Low
High
X
X
High
X
X
X
High
High
High
High
Low
High
High
High
Active
Standby
CMOS Standby
Battery Back-Up
V
CC
EX
Low
A
Low
E1
CON
Low
E2
CON
High
Power
Active
Note: 1. X = V
IH
or V
IL
.
2. V
SO
= Battery Back-up Switchover Voltage. (See Table 7 for details).
3/20
M48T212A
Figure 3. Hardware Hookup
A0-A18
3.3V
A0-A3
VCC
VCCSW
MOTOROLA
MTD20P06HDL
A0-Axx
VOUT
0.1µF
VCC
CMOS
SRAM
E
0.1µF
1N5817
(1)
A
E
EX
W
G
M48T212A
E1CON
Note 2
E2CON
WDI
RSTIN1
RSTIN2
DQ0-DQ7
VCAP
SuperCap Supply
VSS
XI
RST
IRQ/FT
X0
32 kHz
Crystal
E
VCC
CMOS
SRAM
A0-Axx
AI03049
Note: 1. See description in Power Supply Decoupling and Undershoot Protection.
2. Traces connecting E1
CON
and E2
CON
to external SRAM should be as short as possible.
Figure 4. AC Testing Load Circuit
(3,4)
Table 5. AC Measurement Conditions
Input Rise and Fall Times
≤
5ns
0 to 3V
1.5V
Input Pulse Voltages
Input and Output Timing Ref. Voltages
DEVICE
UNDER
TEST
645Ω
Note that Output Hi-Z is defined as the point where data
is no longer driven.
CL = 100pF or 5pF
(1)
CL = 30 pF
(2)
1.75V
CL includes JIG capacitance
AI03239
Note: 1. DQ0-DQ7
2. E1
CON
and E2
CON
3. Excluding open-drain output pins
4/20
M48T212A
Table 6. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
C
IN
C
OUT (2)
Parameter
Input Capacitance
Input/Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
10
Unit
pF
pF
Note: 1. Sampled only, not 100% tested.
2. Outputs deselected.
Table 7. DC Characteristics
(T
A
= 0 to 70°C; V
CC
= 3V to 3.6V)
Symbol
I
LI (1,2)
I
LO (1)
I
CC
I
CC1
I
CC2
I
BAT
V
IL
V
IH
V
OL
V
OH
V
OHB (4)
I
OUT1 (5)
I
OUT2
V
PFD
V
SO
V
BAT
V
CAP
Note: 1.
2.
3.
4.
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Battery Current OSC ON
Battery Current OSC OFF
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage (open drain)
(3)
Output High Voltage
V
OH
Battery Back-up
V
OUT
Current (Active)
V
OUT
Current (Battery Back-up)
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage
Battery Voltage
Capacitor Voltage
(6)
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
Outputs Open
E = V
IH
E = V
CC
–0.2
Min
Typ
Max
±1
±1
Unit
µA
µA
mA
mA
mA
nA
nA
V
V
V
V
V
4
10
3
2
575
800
100
–0.3
2.0
I
OL
= 2.1mA
I
OL
= 10mA
I
OH
= –1.0mA
I
OUT2
= –1.0µA
V
OUT1
> V
CC
–0.3
V
OUT2
> V
BAT
–0.3
2.7
2.9
V
PFD
–100mV
3.0
V
CC
2.4
2.0
0.8
V
CC
+ 0.3
0.4
0.4
3.6
70
100
3.0
V
mA
µA
V
V
V
V
Outputs deselected.
RSTIN1 and RSTIN2 internally pulled-up to V
CC
through 100KΩ resistor. WDI internally pulled-down to V
SS
through 100KΩ resistor.
For IRQ/FT & RST pins (Open Drain).
Conditioned outputs (E1
CON
- E2
CON
) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-
rents will reduce battery life.
5. External SRAM must match TIMEKEEPER Controller chip V
CC
specification.
6. When fully charged.
5/20
stm32/stm8
