M48Z02
M48Z12
16 Kbit (2Kb x 8) ZEROPOWER
®
SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
UNLIMITED WRITE CYCLES
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z02: 4.50V
≤
V
PFD
≤
4.75V
– M48Z12: 4.20V
≤
V
PFD
≤
4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2K x 8 SRAMs
DESCRIPTION
The M48Z02/12 ZEROPOWER
®
RAM is a 2K x 8
non-volatile static RAM which is pin and functional
compatible with the DS1220.
A special 24 pin 600mil DIP CAPHAT™ package
houses the M48Z02/12 silicon with a long life lith-
ium button cell to form a highly integrated battery
backed-up memory solution.
The M48Z02/12 button cell has sufficient capacity
and storage life to maintain data and clock function-
ality for an accumulated time period of at least 10
years in the absence of power over the operating
temperature range.
Table 1. Signal Names
A0-A10
DQ0-DQ7
E
G
W
V
CC
V
SS
Address Inputs
Data Inputs / Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
24
1
PCDIP24 (PC)
Battery CAPHAT
Figure 1. Logic Diagram
VCC
11
A0-A10
8
DQ0-DQ7
W
E
G
M48Z02
M48Z12
VSS
AI01186
May 1999
1/12
M48Z02, M48Z12
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
STG
T
SLD (2)
V
IO
V
CC
I
O
P
D
Parameter
Ambient Operating Temperature
Storage Temperature (V
CC
Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
Value
–40 to 85
–40 to 85
260
–0.3 to 7
–0.3 to 7
20
1
Unit
°C
°C
°C
V
V
mA
W
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Mode
Deselect
Write
Read
Read
Deselect
Deselect
V
SO
to V
PFD
(min)
≤
V
SO
4.75V to 5.5V
or
4.5V to 5.5V
V
CC
E
V
IH
V
IL
V
IL
V
IL
X
X
G
X
X
V
IL
V
IH
X
X
W
X
V
IL
V
IH
V
IH
X
X
DQ0-DQ7
High Z
D
IN
D
OUT
High Z
High Z
High Z
Power
Standby
Active
Active
Active
CMOS Standby
Battery Back-up Mode
Notes:
X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Figure 2. DIP Pin Connections
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
24
1
23
2
22
3
21
4
20
5
6
M48Z02 19
M48Z12 18
7
17
8
16
9
15
10
11
14
12
13
AI01187
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DESCRIPTION
(cont’d)
The M48Z02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The M48Z02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
2/12
M48Z02, M48Z12
Figure 3. Block Diagram
A0-A10
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
POWER
2K x 8
SRAM ARRAY
DQ0-DQ7
VPFD
E
W
G
VCC
VSS
AI01255
READ MODE
The M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
5ns
0V to 3V
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
3/12
M48Z02, M48Z12
Table 5. Capacitance
(1)
(T
A
= 25
°C)
Symbol
C
IN
C
IO (2)
Parameter
Input Capacitance
Input / Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
10
10
Unit
pF
pF
Notes:
1. Effective capacitance measured with power supply at 5V.
2. Outputs deselected
Table 6. DC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
I
LI (1)
I
LO (1)
I
CC
I
CC1
I
CC2
V
IL (2)
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 2.1mA
I
OH
= –1mA
2.4
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
Outputs open
E = V
IH
E = V
CC
– 0.2V
–0.3
2.2
Min
Max
±1
±5
80
3
3
0.8
V
CC
+ 0.3
0.4
Unit
µA
µA
mA
mA
mA
V
V
V
V
Notes:
1. Outputs Deselected.
2. Negative spikes of –1V allowed for up to 10ns once per cycle.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70°C or –40 to 85°C)
Symbol
V
PFD
V
PFD
V
SO
t
DR
Parameter
Power-fail Deselect Voltage (M48Z02)
Power-fail Deselect Voltage (M48Z12)
Battery Back-up Switchover Voltage
Expected Data Retention Time
10
Min
4.5
4.2
Typ
4.6
4.3
3.0
Max
4.75
4.5
Unit
V
V
V
YEARS
Note:
1. All voltages referenced to V
SS
.
4/12
M48Z02, M48Z12
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C)
Symbol
t
PD
t
F (1)
t
FB (2)
t
R
t
RB
t
REC
Parameter
E or W at V
IH
before Power Down
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
V
PFD
(min) to V
SO
V
CC
Fall Time
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
V
SO
to V
PFD
(min) V
CC
Rise Time
E or W at V
IH
after Power Up
Min
0
300
10
0
1
2
Max
Unit
µs
µs
µs
µs
µs
ms
Notes:
1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 50
µs
after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SO
fall time of less than t
FB
may cause corruption of RAM data.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tPD
INPUTS
RECOGNIZED
tDR
tFB
tRB
DON'T CARE
tR
tREC
NOTE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note:
Inputs may or may not be recognized at this time. Caution should be taken to keep E high as V
CC
rises past V
PFD
(min). Some systems
may perform inadvertent write cycles after V
CC
rises above V
PFD
(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/12
