M50FW020
2 Mbit (256Kb x8, Uniform Block)
3V Supply Firmware Hub Flash Memory
PRODUCT PREVIEW
s
SUPPLY VOLTAGE
– V
CC
= 3V to 3.6V for Program, Erase and
Read Operations
– V
PP
= 12V for Fast Program and Fast Erase
(optional)
s
TWO INTERFACES
– Firmware Hub (FWH) Interface for embedded
operation with PC Chipsets
– Address/Address Multiplexed (A/A Mux) In-
terface for programming equipment compati-
bility
PLCC32 (K)
s
FIRMWARE HUB (FWH) HARDWARE
INTERFACE MODE
– 5 Signal Communication Interface supporting
Read and Write Operations
– Hardware Write Protect Pins for Block
Protection
– Register Based Read and Write Protection
– 5 Additional General Purpose Inputs for
platform design flexibility
– Synchronized with 33MHz PCI clock
– Multi-byte Read Operation (1-byte, 16-byte,
32-byte)
ID0-ID3
5
FGPI0-
FGPI4
FWH4
CLK
IC
RP
INIT
M50FW020
WP
TBL
4
VCC VPP
4
FWH0-
FWH3
Figure 1. Logic Diagram (FWH Interface)
s
PROGRAMMING TIME
– 10µs typical
– Quadruple Byte Programming Option
s
s
4 UNIFORM 64 Kbyte MEMORY BLOCKS
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program and Block Erase
algorithms
– Status Register Bits
s
s
s
PROGRAM and ERASE SUSPEND
FOR USE in PC BIOS APPLICATIONS
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 28h
VSS
AI05427
October 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/33
M50FW020
Figure 2. Logic Diagram (A/A Mux Interface)
DESCRIPTION
The M50FW020 is a 2 Mbit (256Kb x8) non-
volatile memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface, the Firmware Hub
(or FWH) Interface, uses Intel’s proprietary FWH
protocol. This has been designed to remove the
VCC VPP
11
A0-A10
8
DQ0-DQ7
RC
IC
G
W
RP
M50FW020
RB
VSS
AI05428
Figure 3. PLCC Connections
A8
A9
RP
VPP
VCC
RC
A10
A/A Mux
A/A Mux
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
FGPI2
FGPI3
RP
VPP
VCC
CLK
FGPI4
1 32
FGPI1
FGPI0
WP
TBL
ID3
ID2
ID1
ID0
FWH0
IC (VIL)
NC
NC
VSS
VCC
INIT
FWH4
RFU
RFU
IC (VIH)
NC
NC
VSS
VCC
G
W
RB
DQ7
9
M50FW020
25
17
FWH1
FWH2
VSS
FWH3
RFU
RFU
RFU
A/A Mux
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
A/A Mux
AI05432
Note: Pins 27 and 28 are not internally connected.
2/33
M50FW020
need for the ISA bus in current PC Chipsets; the
M50FW020 acts as the PC BIOS on the Low Pin
Count bus for these PC Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in PLCC32 package and it
is supplied with all the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Input/Output Communications (FWH0-FWH3).
All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (FWH4).
The In-
put Communication Frame (FWH4) signals the
start of a bus operation. When Input Communica-
tion Frame is Low, V
IL
, on the rising edge of the
Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
IL
, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, V
IH
, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3).
The
Identification Inputs select the address that the
memory responds to. Up to 16 memories can be
addressed on a bus. For an address bit to be ‘0’
the pin can be left floating or driven Low, V
IL
; an
internal pull-down resistor is included with a value
of R
IL
. For an address bit to be ‘1’ the pin must be
driven High, V
IH
; there will be a leakage current of
I
LI2
through each pin when pulled to V
IH
; see Table
19.
By convention the boot memory must have
address ‘0000’ and all additional memories take
sequential addresses starting from ‘0001’.
Table 1. Signal Names (FWH Interface)
FWH0-FWH3
FWH4
ID0-ID3
FGPI0-FGPI4
IC
RP
INIT
CLK
TBL
WP
RFU
V
CC
V
PP
V
SS
NC
Input/Output Communications
Input Communication Frame
Identification Inputs
General Purpose Inputs
Interface Configuration
Interface Reset
CPU Reset
Clock
Top Block Lock
Write Protect
Reserved for Future Use. Leave
disconnected or set at V
IL
or V
IH
.
Supply Voltage
Optional Supply Voltage for Fast
Erase Operations
Ground
Not Connected Internally
General Purpose Inputs (FGPI0-FGPI4).
The Gen-
eral Purpose Inputs can be used as digital inputs
for the CPU to read. The General Purpose Input
Register holds the values on these pins. The pins
must have stable data from before the start of the
cycle that reads the General Purpose Input Regis-
ter until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
V
IL,
or High, V
IH
.
Interface Configuration (IC).
The Interface Con-
figuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, V
IL
; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
IH
. An internal pull-down resistor is
included with a value of R
IL
; there will be a leakage
current of I
LI2
through each pin when pulled to V
IH
;
see Table 19.
3/33
M50FW020
Table 2. Signal Names (A/A Mux Interface)
IC
A0-A10
DQ0-DQ7
G
W
RC
RB
RP
V
CC
V
PP
V
SS
NC
Interface Configuration
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
Row/Column Address Select
Ready/Busy Output
Interface Reset
Supply Voltage
Optional Supply Voltage for Fast
Program and Fast Erase
Operations
Ground
Not Connected Internally
Interface Reset (RP).
The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
IL
, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
IH
, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT).
The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK).
The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL).
The Top Block Lock
input is used to prevent the Top Block (Block 3)
from being changed. When Top Block Lock, TBL,
is set Low, V
IL
, Program and Erase operations in
the Top Block have no effect, regardless of the
state of the Lock Register. When Top Block Lock,
TBL, is set High, V
IH
, the protection of the Block is
determined by the Lock Register. The state of Top
Block Lock, TBL, does not affect the protection of
the Main Blocks (Blocks 0 to 2).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Erase operation is initiated and must not
be changed until the operation completes or un-
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
TBL during Program or Erase Suspend.
Write Protect (WP).
The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 2)
from being changed. When Write Protect, WP, is
set Low, V
IL
, Program and Erase operations in the
Main Blocks have no effect, regardless of the state
of the Lock Register. When Write Protect, WP, is
set High, V
IH
, the protection of the Block is
determined by the Lock Register. The state of
Write Protect, WP, does not affect the protection of
the Top Block (Block 3).
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated and must not be
changed until the operation completes or unpre-
dictable results may occur. Care should be taken
to avoid unpredictable behavior by changing WP
during Program or Erase Suspend.
Reserved for Future Use (RFU).
These pins do
not have assigned functions in this revision of the
part. They may be left disconnected or driven Low,
V
IL
, or High, V
IH
.
Address/Address Multiplexed (A/A Mux)
Signal Descriptions
For the Address/Address Multiplexed (A/A Mux)
Interface see Figure 2, Logic Diagram (A/A Mux
Interface), and Table 2, Signal Names (A/A Mux
Interface).
Address Inputs (A0-A10).
The Address Inputs
are used to set the Row Address bits (A0-A10) and
the Column Address bits (A11-A17). They are
latched during any bus operation by the Row/Col-
umn Address Select input, RC.
Data Inputs/Outputs (DQ0-DQ7).
The Data In-
puts/Outputs hold the data that is written to or read
from the memory. They output the data stored at
the selected address during a Bus Read opera-
tion. During Bus Write operations they represent
the commands sent to the Command Interface of
the internal state machine. The Data Inputs/Out-
puts, DQ0-DQ7, are latched during a Bus Write
operation.
Output Enable (G).
The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W).
The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Row/Column Address Select (RC).
The Row/
Column Address Select input selects whether the
Address Inputs should be latched into the Row
Address bits (A0-A10) or the Column Address bits
(A11-A17). The Row Address bits are latched on
the falling edge of RC whereas the Column
Address bits are latched on the rising edge.
4/33
M50FW020
Table 3. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
PP
Parameter
Ambient Operating Temperature (Temperature Range Option 1)
Ambient Operating Temperature (Temperature Range Option 5)
Temperature Under Bias
Storage Temperature
Input or Output Voltage
Supply Voltage
Program Voltage
Value
0 to 70
–20 to 85
–50 to 125
–65 to 150
–0.6 to V
CC
+ 0.6
–0.6 to 4
–0.6 to 13
Unit
°C
°C
°C
°C
V
V
V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V and for less than 20ns during transitions. Maximum Voltage may overshoot to V
CC
+ 2V
and for less than 20ns during transitions.
Ready/Busy Output (RB).
The Ready/Busy pin
gives the status of the memory’s Program/Erase
Controller. When Ready/Busy is Low, V
OL
, the
memory is busy with a Program or Erase operation
and it will not accept any additional Program or
Erase command except the Program/Erase
Suspend command. When Ready/Busy is High,
V
OH
, the memory is ready for any Read, Program
or Erase operation.
Supply Signal Descriptions
The Supply Signals are the same for both interfac-
es.
V
CC
Supply Voltage.
The V
CC
Supply Voltage
supplies the power for all operations (Read, Pro-
gram, Erase etc.).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from
accidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the
memory contents being altered will be invalid.
After V
CC
becomes valid the Command Interface
is reset to Read mode.
A 0.1µF capacitor should be connected between
the V
CC
Supply Voltage pins and the V
SS
Ground
pin to decouple the current surges from the power
supply. Both V
CC
Supply Voltage pins must be
connected to the power supply. The PCB track
widths must be sufficient to carry the currents
required during program and erase operations.
V
PP
Optional Supply Voltage.
The V
PP
Optional
Supply Voltage pin is used to select the Fast
Program (see the Quadruple Byte Program
Command description) and Fast Erase options of
the memory and to protect the memory. When V
PP
< V
PPLK
Program and Erase operations cannot be
performed and an error is reported in the Status
Register if an attempt to change the memory
contents is made. When V
PP
= V
CC
Program and
Erase operations take place as normal. When V
PP
= V
PPH
Fast Program (if A/A Mux interface is
selected) and Fast Erase operations are used.
Any other voltage input to V
PP
will result in
undefined behavior and should not be used.
V
PP
should not be set to V
PPH
for more than 80
hours during the life of the memory.
V
SS
Ground.
V
SS
is the reference for all the volt-
age measurements.
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