E2L0034-17-Y1
¡ Semiconductor
MSM5412222
¡ Semiconductor
262,214-Word
¥
12-Bit Field Memory
This version: Jan. 1998
MSM5412222
Previous version: Dec. 1996
Pr
el
im
in
ar
y
DESCRIPTION
The OKI MSM5412222 is a high performance 3-Mbit, 256K
¥
12-bit, Field Memory. It is especially
designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs,
VTRs, digital movies and Multi-media systems. MSM5412222 is a FRAM for wide or low end use
in general commodity TVs and VTRs exclusively. MSM5412222 is not designed for high end use
in medical systems, professional graphics systems which require long term picture storage, data
storage systems and others. Two or more MSM5412222s can be cascaded directly without any
delay devices between them. (Cascading provides larger storage depth or a longer delay).
Each of the 12-bit planes has separate serial write and read ports. These employ independent
control clocks to support asynchronous read and write operations. Different clock rates are also
supported, which allow alternate data rates between write and read data streams.
The MSM5412222 provides high speed FIFO, First-In First-Out, operation without external
refreshing: MSM5412222 refreshes its DRAM storage cells automatically, so that it appears fully
static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free
serial access operation, so that serial read and/or write control clock can be halted high or low
for any duration as long as the power is on. Internal conflicts of memory access and refreshing
operations are prevented by special arbitration logic.
The MSM5412222’s function is simple, and similar to a digital delay device whose delay-bit-
length is easily set by reset timing. The delay length, and the number of read delay clocks
between write and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256
¥
12-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.
Additionally, the MSM5412222 has a write mask function or input enable function (IE), and read-
data skipping function or output enable function (OE). The differences between write enable
(WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE
and RE can stop serial write/read address increments, but IE and OE cannot stop the increment,
when write/read clocking is continuously applied to MSM5412222. The input enable (IE)
function allows the user to write into selected locations of the memory only, leaving the rest of
the memory contents unchanged. This facilitates data processing to display a “picture in picture”
on a TV screen.
The MSM5412222 is similar in operation and functionality to OKI 1-Mbit Field Memory
MSM514222B and 2-Mbit Field Memory MSM518222. Three MSM514222Bs or one MSM514222B
plus one MSM518222 can be replaced simply by one MSM5412222.
1/15
¡ Semiconductor
MSM5412222
FEATURES
• Single power supply : 5 V
±10%
• 512 Rows
¥
512 Columns
¥
12 bits
• Fast FIFO (First-In First-Out) operation
• High speed asynchronous serial access
Read/write cycle time
25 ns/30 ns
Access time
23 ns/25 ns
• Direct cascading capability
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package options:
44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM5412222-xxTS-K)
40-pin 400 mil plastic SOJ
(SOJ40-P-400-1.27)
(Product : MSM5412222-xxJS)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM5412222-25TS-K
MSM5412222-30TS-K
MSM5412222-25JS
MSM5412222-30JS
Access Time (Max.)
23 ns
25 ns
23 ns
25 ns
Cycle Time (Min.)
25 ns
30 ns
25 ns
30 ns
Package
400 mil 44-pin TSOP (II)
400 mil 40-pin SOJ
2/15
¡ Semiconductor
MSM5412222
PIN CONFIGURATION (TOP VIEW)
V
SS
D
IN
11
D
IN
10
NC
D
IN
9
D
IN
8
D
IN
7
D
IN
6
NC
D
IN
5
D
IN
4
D
IN
3
D
IN
2
NC
D
IN
1
D
IN
0
SWCK
RSTW
NC
WE
IE
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
D
OUT
11
D
OUT
10
NC
D
OUT
9
D
OUT
8
D
OUT
7
D
OUT
6
NC
D
OUT
5
D
OUT
4
D
OUT
3
D
OUT
2
V
SS
D
OUT
1
D
OUT
0
SRCK
RSTR
NC
RE
OE
V
CC
V
SS
NC
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SS
NC
D
OUT
11
D
OUT
10
D
OUT
9
D
OUT
8
D
OUT
7
D
OUT
6
D
OUT
5
D
OUT
4
D
OUT
3
D
OUT
2
D
OUT
1
D
OUT
0
SRCK
RSTR
RE
OE
V
SS
V
CC
D
IN
11
D
IN
10
D
IN
9
D
IN
8
D
IN
7
D
IN
6
D
IN
5
D
IN
4
D
IN
2
D
IN
1
D
IN
0
10
11
12
13
14
15
16
17
18
19
20
D
IN
3
SWCK
WE
IE
44-Pin Plastic TSOP (II)
(K Type)
RSTW
NC
V
CC
40-Pin Plastic SOJ
Pin Name
SWCK
SRCK
WE
RE
IE
OE
RSTW
RSTR
D
IN
0 - 11
D
OUT
0 - 11
V
CC
V
SS
NC
Function
Serial Write Clock
Serial Read Clock
Write Enable
Read Enable
Input Enable
Output Enable
Write Reset Clock
Read Reset Clock
Data Input
Data Output
Power Supply (5 V)
Ground (0 V)
No Connection
Note: The same power supply voltage must be provided to every V
CC
pin, and the same GND
voltage level must be provided to every V
SS
pin.
3/15
D
OUT
(¥ 12)
RSTR
SRCK
OE
RE
BLOCK DIAGRAM
¡ Semiconductor
Data-out
Buffer (¥ 12)
Serial
Read
Controller
512 Word Serial Read Register (¥ 12)
Read Line Buffer
Low-Half (¥ 12)
256 (¥ 12)
256 (¥ 12)
Read Line Buffer
High-Half (¥ 12)
71 Word
Sub-Register (¥ 12)
256K (¥ 12)
Memory
Array
X
Decoder
Read/Write
and Refresh
Controller
71 Word
Sub-Register (¥ 12)
256 (¥ 12)
Write Line Buffer
Low-Half (¥ 12)
512 Word Serial Write Register (¥ 12)
V
BB
Generator
Serial
Read
Controller
Write Line Buffer
High-Half (¥ 12)
256 (¥ 12)
Clock
Oscillator
Data-in
Buffer (¥ 12)
MSM5412222
D
IN
(¥ 12)
IE
WE
RSTW
SWCK
4/15
¡ Semiconductor
MSM5412222
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is
accomplished by cycling SWCK, and holding WE high after the write address pointer reset
operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e.
SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time
is stored in the serial data registers attached to the DRAM array, an RSTW operation is required
after the last SWCK cycle.
Note that every write timing of MSM5412222 is delayed by one clock compared with read timings
for easy cascading without any interface delay devices.
Write Reset : RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters
to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write
reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states
of WE and IE are ignored in the write reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least
two SWCK cycles.
Data Inputs : D
IN
0 - 11
Write Clock : SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write
address pointer. Data-in setup time t
DS
, and hold time t
DH
are referenced to the rising edge of
SWCK.
Write Enable : WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low
level disables the input and holds the internal write address pointer. There are no WE disable
time (low) and WE enable time (high) restrictions, because the MSM5412222 is in fully static
operation as long as the power is on. Note that WE setup and hold times are referenced to the
rising edge of SWCK.
Input Enable : IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal
write address pointer is always incremented by cycling SWCK regardless of the IE level. Note
that IE setup and hold times are referenced to the rising edge of SWCK.
5/15
