M5450
M5451
LED DISPLAY DRIVERS
FEATURES SUMMARY
■
M5450 34 OUTPUTS/15mA SINK
■
■
Figure 1. Packages
M5451 35 OUTPUTS/15mA SINK
CURRENT GENERATOR OUTPUTS (NO
EXTERNAL RESISTORS REQUIRED)
CONTINUOUS BRIGHTNESS CONTROL
SERIAL DATA INPUT
ENABLE (ON M5450)
WIDE SUPPLY VOLTAGE OPERATION
TTL COMPATIBILITY
40
■
■
■
■
■
1
PDIP40
(Plastic Package)
Application Examples:
■
MICROPROCESSOR DISPLAYS
■
■
■
INDUSTRIAL CONTROL INDICATOR
RELAY DRIVER
INSTRUMENTATION READOUTS
DESCRIPTION
The M5450 and M5451 are monolithic MOS inte-
grated circuits produced with an N-channel silicon
gate technology. They are available in 40-pin dual
in-line plastic packages.
A single pin controls the LED display brightness by
setting a reference current through a variable re-
sistor connected to V
DD
or to a separate supply of
13.2V maximum.
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PLCC44
(Plastic Chip Carrier)
REV. 2
April 2004
1/12
M5450, M5451
Figure 2. Pin Connection
OUTPUT BIT 14
OUTPUT BIT 15
OUTPUT BIT 16
OUTPUT BIT 17
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
42
V
SS
OUTPUT BIT 17
OUTPUT BIT 16
OUTPUT BIT 15
OUTPUT BIT 14
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
OUTPUT BIT 3
OUTPUT BIT 2
OUTPUT BIT 1
BRIGHTNESS CONTROL
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OUTPUT BIT 18
OUTPUT BIT 19
OUTPUT BIT 20
OUTPUT BIT 21
OUTPUT BIT 22
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
OUTPUT BIT 33
OUTPUT BIT 34
DATA ENABLE FOR M5450
OUTPUT BIT 35 FOR M5451
DATA IN
CLOCK IN
N.C
44
43
41
OUTPUT BIT 21
V
SS
OUTPUT BIT 13
OUTPUT BIT 12
OUTPUT BIT 11
OUTPUT BIT 10
OUTPUT BIT 9
N.C.
OUTPUT BIT 8
OUTPUT BIT 7
OUTPUT BIT 6
OUTPUT BIT 5
OUTPUT BIT 4
40
6
5
4
3
2
1
OUTPUT BIT 22
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
OUTPUT BIT 23
OUTPUT BIT 24
OUTPUT BIT 25
OUTPUT BIT 26
OUTPUT BIT 27
N.C.
OUTPUT BIT 28
OUTPUT BIT 29
OUTPUT BIT 30
OUTPUT BIT 31
OUTPUT BIT 32
18
19
21
22
23
24
25
26
20
27
OUTPUT BIT 34
Figure 3. Block Diagram
V
DD
BRIGTHNESS
CONTROL
100kΩ
bs
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DATA ENABLE (M5450)
OUTPUT35 (5451)
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SERIAL
DATA
CLOCK
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23
22
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OUTPUT
BIT 34
24
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OUTPUT
BIT 1
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OUTPUT BIT 33
BRIGHTNESS CONTROL
OUTPUT BIT 3
OUTPUT BIT 1
OUTPUT BIT 2
N.C
35 OUTPUT BUFFERS
LOAD
35 LATCHES
35-BIT SHIFT REGISTER
RESET
21
1
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DATA IN
OUTPUT BIT 35
CLOCK IN
V
DD
28
M5450, M5451
Table 1. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
O(off)
I
O
P
TOT
T
j
T
OP
T
STG
Supply Voltage
Input Voltage
Off State Output Voltage
Output Sink Current
Total Package Power Dissipation at 25°C
Total Package Power Dissipation at 85°C
Junction Temperature
Operating Temperature Range
Storage Temperature Range
Parameter
Value
– 0.3 to 15
– 0.3 to 15
15
40
1
560
150
– 25 to 85
– 65 to 150
Unit
V
V
V
mA
W
mW
°C
°C
°C
Note: Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
O
FUNCTIONAL DESCRIPTION
Both the M5450 and the M5451 are specially de-
signed to operate 4 or 5-digit alphanumeric dis-
plays with minimal interface with the display and
the data source. Serial data transfer from the data
source to the display driver is accomplished with 2
signals, serial data and clock. Using a format of a
leading "1" followed by the 35 data bits allows data
transfer without an additional load signal. The 35
data bits are latched after the 36th bit is complete,
thus providing non-multiplexed, direct drive to the
display.
Outputs change only if the serial data bits differ
from the previous time.
Display brightness is determined by control of the
output current LED displays.
A 1nF capacitor should be connected to bright-
ness control, pin 19, to prevent possible oscilla-
tions.
A block diagram is shown in Figure 3. For the
M5450 a DATA ENABLE is used instead of the
35th output. The DATA ENABLE input is a metal
option for the M5450.
The output current is typically 20 times greater
than the current into pin 19, which is set by an ex-
ternal variable resistor. There is an internal limiting
resistor of 400W nominal value.
Figure 4 shows the input data format. A start bit of
logical "1" precedes the 35 bits of data. At the 36th
clock a LOAD signal is generated synchronously
with the high state of the clock, which loads the 35
bits of the shift registers into the latches.
At the low state of the clock a RESET signal is
generated which clears all the shift registers for
the next set of data. The shift registers are static
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master-slave configurations. There is no clear for
the master portion of the first shift register, thus al-
lowing continuous operation.
There must be a complete set of 36 clocks or the
shift registers will not clear.
When power is first applied to the chip an internal
power ON reset signal is generated which resets
all registers and all latches. The START bit and the
first clock return the chip to its normal operation.
Bit 1 is the first bit following the start bit and it will
appear on Pin 18. A logical "1" at the input will turn
on the appropriate LED.
Figure 5 shows the timing relationship between
Data, Clock and DATA ENABLE.
A max clock frequency of 0.5MHz is assumed. For
applications where a lesser number of outputs are
used, it is possible to either increase the current
per output or operate the part at higher than 1V
V
OUT
.
The following equation can be used for calcula-
tions.
T
j
= [(V
OUT
) (I
LED
) (No. of segments) + (V
DD
×
7mA)] (124°C/W) + T
amb
where :
T
j
= junction temperature (150°C max)
V
OUT
= the voltage at the LED driver outputs
I
LED
= the LED current
124°C/W = thermal coefficient of the package
T
amb
= ambient temperature
The above equation was used to plot Figure 6, Fig-
ure 7 and Figure 8.
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M5450, M5451
Table 2. Static Electrical Characteristics
(T
amb
within operating range, V
DD
= 4.75V to 13.2V, V
SS
= 0V, unless otherwise specified)
Symbol
V
DD
I
DD
V
I
Parameter
Supply Voltage
Supply Current
Input Voltage Logical "0" Level
Logical "1" Level
I
B
V
B
V
O(off)
I
O
Brightness Input Current (note 2)
Brightness Input Voltage (pin 19) Input Current = 750µA, T
amb
= 25°C
Off State Out. Voltage
Out. Sink Current (note 3)
Segment OFF
Segment ON
V
O
= 3V
V
O
= 1V (note 4)
Brightness In. = 0µA
Brightness In. = 100µ
Brightness In. = 750µA
f
clock
I
O
Note: 1.
2.
3.
4.
Test Conditions
V
DD
= 13.2V
± 10µA Input Bias
4.75
≤
V
DD
≤
5.25
V
DD
> 5.25
Min.
4.75
- 0.3
2.2
V
DD
- 2
0
3
Typ.
Max.
13.2
7
0.8
V
DD
V
DD
0.75
4.3
13.2
10
Unit
V
mA
V
V
V
mA
V
V
µA
µA
mA
mA
%
0
10
27
15
4
25
2
12
0
Input Clock Frequency
Output Matching (note 1)
Output matching is calculated as the percent variation from I
MAX
+ I
MIN
/2.
With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.
Absolute maximum for each output should be limited to 40mA.
The V
O
voltage should be regulated by the user. See Figure 7 and Figure 8 for allowable VO versus IO operation.
Figure 4. Input Data Format
1
CLOCK
START
DATA
BIT 1
LOAD
(INTERNAL)
RESET
(INTERNAL)
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0.5
± 20
MHz
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BIT 35
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M5450, M5451
Figure 5.
Figure 6.
P
tot
(W)
15mA/segment
34 segments
V
O
= 1V
1.0
CLOCK
0.8
DATA
300ns (min.)
0.6
0.4
0.2
100ns (min.)
SAFE OPERATING
AREA
T
amb
(˚C)
DATA ENABLE
0
20
40
60
80
100
Figure 7.
V
O
(V)
Figure 8.
I0 (mA)
3.2
105
2.8
2.4
2.0
20 segments
30 segments
34 segments
85
65
1.6
1.2
0.8
0.4
T
amb
= 85˚C
T
j
= 150˚C (max.)
˚
4
8
12
16
20
I
LED
(mA)
0
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T
amb
= 85˚C
I
O (max.)
= 40mA
V
O
= 1V
V
O
= 1.5V
V
O
= 2V
N˚ Segm.
5
4
16 20
24
28 32
32
36
40
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