MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M54992 is a semiconductor integrated circuit consisting of 24
stages of CMOS shift registers and latches with serial inputs and
serial or parallel outputs. It is based on Bi-CMOS process
technology, and has 24 bipolar drivers at the parallel outputs.
PIN CONFIGURATION (TOP VIEW)
GND 1
O
6
2
O
5
3
36 GND
35 O
7
Parallel outputs
34 O
8
33 NC
32 O
9
31 O
10
30 O
11
29 O
12
Parallel outputs
O
4
4
Parallel outputs
O
3
5
O
2
6
O
1
7
Serial input
Clock
S-IN
8
FEATURES
q
Serial input and serial or parallel output
q
Serial output enables cascade connection
q
Built-in latch for each stage
q
Enable input provides output control
q
Low supply current (standby current I
CC
≤1mA)
q
Serial I/O level is compatible with typical CMOS devices
q
Driver features: High withstand voltage (BV
CEO
≥30V)
Capable of large drive currents (I
O(max)
=100mA)
q
Wide operating temperrature range T
a
=-10 – +75°C
M54992P
T 9
28 EN
27 V
CC
26 O
13
25 O
14
Enable input
Latch input LATCH 10
O
24
11
O
23
12
Parallel outputs
O
22
13
Parallel outputs
24 O
15
23 O
16
22 NC
21 O
17
Parallel outputs
20 O
18
19 GND
O
21
14
NC 15
APPLICATION
Dot drivers of thermal printer heads, serial/parallel conversion.
Drivers for relays and solenoids.
Parallel outputs
O
20
16
O
19
17
FUNCTION
The M54992 consists of 24 stages of D-type flip flops connected to
24 latches.
Data is input to serial input S-IN, and clock pulses are input to
clock input T. When the clock changes from low to high, the input
data enters the first shift register and data already in the shift
registers is shifted sequentially.
The serial output S-OUT is used to connect multiple M54992 to
expand the number of parallel outputs. S-OUT is connected to S-IN
of the next stage.
For parallel output. When the clock pulse changes from low to
high, latch input (LATCH) is high and output enable input (EN) is
low the serial input data at S-IN appears at output O
1
and the other
data already present is shifted sequentially to outputs O
2
through
O
24
.
The parallel outputs are inverted.
When the latch input is held low, the latch retains the stored data.
When the EN input is high, outputs O
1
through O
24
all turn off. As
the internal logic is unstable when the power is turned on, the EN
input should be kept high (setting outputs O
1
through O
24
off) until
input data is set and the internal logic is initialized.
L-GND is the GND of CMOS logic circuit and P-GND is the GND of
output driver circuits O
1
through O
24
which employ bipolar
transistors capable of large drive currents.
An output load prevention circuit is built in this IC to prevent
misoperation at power ON/OFF. Therefore, when V
CC
falls short of
the fixed level, all outputs (O
1
– O
24
) are compulsorily set to the
OFF state.
Serial input
Clock
Parallel outputs
Parallel outputs
Enable input
GND 18
Outline 36P4E
EN
1
36 V
CC
35 O
13
34 O
14
33 O
15
32 O
16
31 O
17
30 O
18
29
28
27
26 O
19
25 O
20
24 O
21
23 O
22
22 O
23
21 O
24
20 SO
Serial input
Parallel outputs
GND
Parallel outputs
O
12
2
O
11
3
O
10
4
O
9
5
O
8
6
O
7
7
8
GND
9
10
O
6
11
O
5
12
O
4
13
O
3
14
O
2
15
O
1
16
S-IN 17
T 18
Outline 36P2R-A
M54992FP
19 LATCH Latch input
NC: no connection
MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
BLOCK DIAGRAM
Parallel outputs
O
1
O
2
O
3
O
4
O
5
O
6
–
–
O
12
O
13
–
–
O
19
O
20
O
21
O
22
O
23
O
24
Q
L
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
L
Q
D
LATCH
Latch input
Output misoperation
prevention circuit
S-IN Serial input
D
T
Q
D
T
Q
D
T
Q
D
T
Q
D
T
Q
D
T
Q
D
T
Q
D
T
Q
D
T
Q
D
T
Q
TRUTH TABLE
S-IN
L
L
H
H
H
Input
Output
O
1
–O
24
EN
LATCH
T
S-OUT
L
L
IN
L
t-1
L
H
IN
L
L
L
L
IN
H
t-1
L
H
IN
H
H
H
H
IN
H
L
T: IN means to input following signal
1
2
23
24
T Clock
L : low level
H : high level
t-1 : previous state
H output : OFF state
L output : ON state
S-OUT Serial output
(M54992FP)
V
CC
Power supply
GND
EN
Enable input
MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
INPUT/OUTPUT CIRCUIT DIAGRAM
1
Inputs with pullup resistor
(EN, LATCH)
2
Inputs with pulldown resistor
(T, S-IN)
V
CC
V
CC
R
IN
R
IN
GND
GND
3
Serial output (M54992FP)
(S-OUT)
4
Parallel outputs
(O
1
– O
24
)
V
CC
V
CC
GND
GND
MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
ABSOLUTE MAXIMUM RATINGS
(Ta=-10 to 75°C, unless otherwise noted)
Symbol
V
CC
V
I
V
O
I
O
P
d
T
opr
T
stg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Ta=25°C
Mounted on a board
M54992P
M54992FP
S-OUT
O
1
– O
24
: OFF
M54992FP
Parameter
Conditions
Ratings
-0.5 – 8
-0.5 – V
CC
+0.5
-0.5 – V
CC
+0.5
-0.5 – 30
120
2.0
1.9
-10 – 75
-55 – 125
Unit
V
V
V
V
mA
W
W
°C
°C
RECOMMENDED OPERATING CONDITION
(Ta=-10 to 75°C, unless otherwise noted)
Symbol
V
CC
V
O
I
O
Parameter
Supply voltage
Output apply voltage
Output current (per circuit)
Test conditions
Min.
4
O
1
– O
24
: OFF
O
1
– O
24
: ON
Duty cycle : 50% or below
Limits
Typ.
5
Max.
6
30
100
Unit
V
V
mA
ELECTRICAL CHARACTERISTICS
(Ta=25°C, V
CC
=5V, unless otherwise noted)
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OH
I
OL
V
OL1
V
OL2
I
OLK
I
CC1
Supply current
I
CC2
V
T+
V
T-
Misoperation prevention supply voltage.
One driver output is ON.
—
2.9
2.6
3.5
3.4
3.1
5.0
3.9
3.6
mA
V
V
Parameter
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
Low-level output voltage
Output leak current
Test conditions
Ta=-10 – 75°C, V
CC
=4 – 6V
T, S-IN
EN, LATCH
|I
O
|≤1µA
M54992FP (S-OUT)
V
OH
=4.5V
V
OL
=0.4V
I
OL
=100mA
O
1
– O
24
I
OL
=80mA
O
1
– O
24
V
O
=30V(output: OFF) O
1
– O
24
Input: open
All driver outputs are OFF.
V
IH
=5V
V
IL
=0V
Min.
0.7V
CC
0
—
—
4.9
—
-100
400
—
—
—
—
Limits
Typ.
Max.
V
CC
0.3V
CC
25
-25
—
0.1
—
—
0.55
0.4
50
1
Unit
V
V
µA
µA
V
V
µA
µA
V
V
µA
mA
TIMING REQUIREMENTS
(Ta=-10 to 75°C, unless otherwise noted)
Symbol
f
(T)
t
w(T)
t
w(L)
t
su
t
h
t
d(T-L)
t
r(T)
t
f(T)
Parameter
Clock frequency
Clock pulse width
Latch pulse width
Data setup time
Data hold time
Clock-latch time
Clock pulse rise time
Clock pulse fall time
Test conditions
Input duty cycle: 45 – 55%
100
100
50
20
400
500
500
Min.
Limits
Typ.
Max.
4
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI <CONTROL / DRIVER IC>
M54992P/FP
Bi-CMOS 24-BIT SERIAL-INPUT LATCHED DRIVER
TIMING CHART
Serial input
S-IN
2.5V
2.5V
t
su
t
h
90%
Clock input
T
2.5V
2.5V
10%
t
w(T)
t
r(T)
t
d(T-L)
Latch input LATCH
90%
10%
t
f
(T)
2.5V
2.5V
t
w(L)
SWITCHING CHARACTERISTICS
(Ta=25°C, V
CC
=5V, unless otherwise noted)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Low-to-high-level output propagation time
From input T to output S-OUT
High-to-low-level output propagation time
From input T to output S-OUT
Low-to-high-level output propagation time
From input T to output ON
High-to-low-level output propagation time
From input T to output ON
Low-to-high-level output propagation time
From input EN to output ON
High-to-low level output propagation time
From input EN to output ON
R
L(S-OUT)
=∞
R
L(ON)
=100Ω
(N=1–24)
C
L
=15pF
5
Test conditions
M54992FP
V
IH
=5V
V
IL
=0V
Min.
Limits
Typ.
Max.
0.2
0.2
10
5
10
Unit
µs
µs
µs
µs
µs
µs
单片机
