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M54HC73D1

RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

器件类别：逻辑    逻辑   

厂商名称：ST(意法半导体)

厂商官网：http://www.st.com/

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参数 预览 参数对比
器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
ST(意法半导体)
零件包装代码
DIP
包装说明
DIP, DIP14,.3
针数
14
Reach Compliance Code
_compli
系列
HC/UH
JESD-30 代码
R-CDIP-T14
JESD-609代码
e0
长度
19 mm
负载电容（CL）
50 pF
逻辑集成电路类型
J-K FLIP-FLOP
最大频率@ Nom-Su
20000000 Hz
最大I（ol）
0.004 A
位数
2
功能数量
2
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
输出极性
COMPLEMENTARY
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装等效代码
DIP14,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度（摄氏度）
NOT SPECIFIED
电源
2/6 V
Prop。Delay @ Nom-Su
38 ns
传播延迟（tpd）
190 ns
认证状态
Not Qualified
座面最大高度
3.7 mm
最大供电电压 (Vsup)
6 V
最小供电电压 (Vsup)
2 V
标称供电电压 (Vsup)
4.5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总剂量
50k Rad(Si) V
触发器类型
NEGATIVE EDGE
宽度
7.62 mm
最小 fmax
24 MHz
文档预览
M54HC73
RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 80MHz (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
=2µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 73
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9203-071
DILC-14
FPC-14
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC73D
M54HC73K
EM
M54HC73D1
M54HC73K1
DESCRIPTION
The M54HC73 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C
2
MOS technology.
Depending on the logic level applied to J and K
inputs, this device changes state on the negative
going transition of clock input pulse (CK). The
clear function is accomplished independently of
the clock condition when the clear input (CLR) is
taken low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/11
M54HC73
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
1, 5
2, 6
12, 9
13, 8
14, 7, 3, 10
11
4
SYMBOL
1CK, 2CK
NAME AND FUNCTION
Clock Input
Asynchronous Reset
1CLR, 2CLR
Inputs
1Q, 2Q
True Flip-Flop Outputs
Complement Flip-Flop
1Q, 2Q
Outputs
1J, 2J, 1K, Synchronous Inputs
2K
Flip-Flop 1 and 2
GND
Ground (0V)
V
CC
Positive Supply Voltage
Table 2: Truth Table
INPUTS
CLR
L
H
H
H
H
H
X : Don’t Care
OUTPUTS
FUNCTION
K
X
L
H
L
H
X
CK
X
Q
L
Q
n
L
H
Q
n
Q
n
Q
H
Q
n
H
L
Q
n
Q
n
CLEAR
NO CHANGE
----
----
TOGGLE
NO CHANGE
J
X
L
L
H
H
X
2/11
M54HC73
Figure 3: Logic Diagram
Table 3: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
25
±
50
300
-65 to +150
265
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Power Dissipation
P
D
T
stg
T
L
Storage Temperature
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 4: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time
V
CC
= 2.0V
V
CC
= 4.5V
V
CC
= 6.0V
Parameter
Value
2 to 6
0 to V
CC
0 to V
CC
-55 to 125
0 to 1000
0 to 500
0 to 400
Unit
V
V
V
°C
ns
ns
ns
3/11
M54HC73
Table 5: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
V
OL
Low Level Output
Voltage
2.0
4.5
6.0
4.5
6.0
I
I
I
CC
Input Leakage
Current
Quiescent Supply
Current
6.0
6.0
I
O
=-20
µA
I
O
=-20
µA
I
O
=-20
µA
I
O
=-4.0 mA
I
O
=-5.2 mA
I
O
=20
µA
I
O
=20
µA
I
O
=20
µA
I
O
=4.0 mA
I
O
=5.2 mA
V
I
= V
CC
or GND
V
I
= V
CC
or GND
T
A
= 25°C
Min.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
4.18
5.68
2.0
4.5
6.0
4.31
5.8
0.0
0.0
0.0
0.17
0.18
0.1
0.1
0.1
0.26
0.26
±
0.1
2
1.9
4.4
5.9
4.13
5.63
0.1
0.1
0.1
0.33
0.33
±
1
20
Typ.
Max.
Value
-40 to 85°C
Min.
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
4.10
5.60
0.1
0.1
0.1
0.40
0.40
±
1
40
µA
µA
V
V
Max.
-55 to 125°C
Min.
1.5
3.15
4.2
0.5
1.35
1.8
Max.
V
Unit
V
IH
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IL
V
V
OH
4/11
M54HC73
Table 6: AC Electrical Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
T
A
= 25°C
Min.
Typ.
30
8
7
42
14
12
54
18
15
15
60
80
18
6
6
21
7
6
30
8
6
Max.
75
15
13
125
25
21
145
29
25
4.8
24
28
75
15
13
75
15
13
75
15
13
0
0
0
75
15
13
95
19
16
95
19
16
95
19
16
0
0
0
95
19
16
Value
-40 to 85°C
Min.
Max.
95
19
16
155
31
26
180
36
31
4
20
24
110
22
19
110
22
19
110
22
19
0
0
0
110
22
19
-55 to 125°C
Min.
Max.
110
22
19
190
38
32
220
44
37
ns
Unit
t
TLH
t
THL
Output Transition
Time
t
PLH
t
PHL
Propagation Delay
Time (CK - Q)
t
PLH
t
PHL
Propagation Delay
Time (CLR - Q)
f
MAX
Maximum Clock
Frequency
Minimum Pulse
Width (CK)
Minimum Pulse
Width (CLR)
Minimum Set-up
Time
Minimum Hold
Time
Minimum Removal
Time
ns
ns
6
30
35
MHz
t
W(H)
t
W(L)
t
W(L)
ns
ns
t
s
ns
t
h
ns
t
REM
25
7
6
ns
Table 7: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
T
A
= 25°C
Min.
Typ.
5
35
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per FLIP/
FLOP)
5/11
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参数对比
与M54HC73D1相近的元器件有：M54HC73D、M54HC73、M54HC73_04、M54HC73K、M54HC73K1。描述及对比如下：
型号 M54HC73D1 M54HC73D M54HC73 M54HC73_04 M54HC73K M54HC73K1
描述 RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
是否无铅 含铅 含铅 - - 含铅 含铅
是否Rohs认证 不符合 不符合 - - 不符合 不符合
厂商名称 ST(意法半导体) ST(意法半导体) - - ST(意法半导体) ST(意法半导体)
零件包装代码 DIP DIP - - DFP DFP
包装说明 DIP, DIP14,.3 DIP, DIP14,.3 - - DFP, FL14,.3 DFP, FL14,.3
针数 14 14 - - 14 14
Reach Compliance Code _compli _compli - - _compli _compli
系列 HC/UH HC/UH - - HC/UH HC/UH
JESD-30 代码 R-CDIP-T14 R-CDIP-T14 - - R-CDFP-F14 R-CDFP-F14
JESD-609代码 e0 e0 - - e0 e0
长度 19 mm 19 mm - - 9.95 mm 9.95 mm
负载电容（CL） 50 pF 50 pF - - 50 pF 50 pF
逻辑集成电路类型 J-K FLIP-FLOP J-K FLIP-FLOP - - J-K FLIP-FLOP J-K FLIP-FLOP
最大频率@ Nom-Su 20000000 Hz 20000000 Hz - - 20000000 Hz 20000000 Hz
最大I（ol） 0.004 A 0.004 A - - 0.004 A 0.004 A
位数 2 2 - - 2 2
功能数量 2 2 - - 2 2
端子数量 14 14 - - 14 14
最高工作温度 125 °C 125 °C - - 125 °C 125 °C
最低工作温度 -55 °C -55 °C - - -55 °C -55 °C
输出极性 COMPLEMENTARY COMPLEMENTARY - - COMPLEMENTARY COMPLEMENTARY
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED - - CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DIP - - DFP DFP
封装等效代码 DIP14,.3 DIP14,.3 - - FL14,.3 FL14,.3
封装形状 RECTANGULAR RECTANGULAR - - RECTANGULAR RECTANGULAR
封装形式 IN-LINE IN-LINE - - FLATPACK FLATPACK
峰值回流温度（摄氏度） NOT SPECIFIED NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED
电源 2/6 V 2/6 V - - 2/6 V 2/6 V
Prop。Delay @ Nom-Su 38 ns 38 ns - - 38 ns 38 ns
传播延迟（tpd） 190 ns 190 ns - - 190 ns 190 ns
认证状态 Not Qualified Not Qualified - - Not Qualified Not Qualified
最大供电电压 (Vsup) 6 V 6 V - - 6 V 6 V
最小供电电压 (Vsup) 2 V 2 V - - 2 V 2 V
标称供电电压 (Vsup) 4.5 V 4.5 V - - 4.5 V 4.5 V
表面贴装 NO NO - - YES YES
技术 CMOS CMOS - - CMOS CMOS
温度等级 MILITARY MILITARY - - MILITARY MILITARY
端子面层 Tin/Lead (Sn/Pb) TIN LEAD - - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 THROUGH-HOLE THROUGH-HOLE - - FLAT FLAT
端子节距 2.54 mm 2.54 mm - - 1.27 mm 1.27 mm
端子位置 DUAL DUAL - - DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED
总剂量 50k Rad(Si) V 50k Rad(Si) V - - 50k Rad(Si) V 50k Rad(Si) V
触发器类型 NEGATIVE EDGE NEGATIVE EDGE - - NEGATIVE EDGE NEGATIVE EDGE
宽度 7.62 mm 7.62 mm - - 6.91 mm 6.91 mm
最小 fmax 24 MHz 24 MHz - - 24 MHz 24 MHz
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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