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M5M29GB640VP

FEATURES

67,108,864-BIT(8,388,608 - WORD BY 8-BIT / 4,194,304 - WORD BY 16-BIT)

3.3V

ONLY FLASH MEMORY

FEATURES

• Single power supply operation

- 3.0V only operation for read, erase and program

operation

- VCC=VPP=2.7~3.6V

- VCC=12 fast production programming

- 1.65V~2.5V or 2.7V~3.6V I/O Option (VCCQ)

- Operating temperature:-40°

C~85°

• Fast access time : 90/120ns

• Low power consumption

- 9mA maximum active read current, f=5MHz (CMOS

input)

- 21mA program erase current maximum

(VPP=1.65~3.6V)

- 7uA typical standby current under power saving

mode

• Sector architecture

- Sector Erase (Sector structure : 4Kword x 2 (boot

sectors), 4Kword x 6 (parameter sectors), 32Kword x

7 (parameter sectors)

• Automatic Suspend Enhance

- Word/byte write suspend to read

- Sector erase suspend to word/byte write

- Sector erase suspend to read register report

• Automatic sector erase, full chip erase, word write and

sector lock/unlock configuration

• Status Reply

- Detection of program and erase operation comple-

tion.

- Command User Interface (CUI)

- Status Register (SR)

• Data Protection Performance

- Include boot sectors and parameter and main sectors

to be block/unblock

• 100,000 minimum erase/program cycles

• Common Flash Interface (CFI)

•

64-bit

Protection Register

Latch-up protected to 100mA from -1V to VCC+1V

- Top Boot

• Auto Erase (chip & sector) and Auto Program

- Automatically program and verify data at specified

address

A15

A14

A13

A12

A11

A10

A21

A20

A19

A18

A17

• Package type:

- 48-pin TSOP (12mm x 20mm)

M5M29GB640VP

A16

VCCQ

GND

Q15

Q14

Q13

Q12

VCC

Q11

Q10

GND

M5M29GB640VP

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The

M5M29GB640VP

uses a 2.7V~3.6V VCC sup-

ply to perform the High Reliability Erase and auto Pro-

gram/Erase algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

tially reduces active current when the device is in static

mode (addresses not switching). In this mode, the typi-

cal ICCS current is 7uA (CMOS) at 3.0V VCC.

As CE and RP are at VCC, ICC CMOS standby mode is

enabled. When RP is at GND, the reset mode is enabled

which minimize power consumption and provide data

write protection.

A reset time (tPHQV) is required from RP switching high

until outputs are valid. Similarly, the device has a wake

time (tPHEL) from RP-high until writes to the CUI are

recognized. With RP at GND, the WSM is reset and the

status register is cleared.

A Command User Interface (CUI) serves as the inter-

face between the system processor and internal opera-

tion of the device. A valid command sequence written to

the CUI initiates device automation. An internal Write

State Machine (WSM) automatically executes the algo-

rithms and timings necessary for erase, full chip erase,

word/byte write and sector lock/unlock configuration op-

erations.

A sector erase operation erases one of the device's 32K-

word sectors typically within 1.0s, 4K-word sectors typi-

cally within 0.5s independent of other sectors. Each sec-

tor can be independently erased minimum 100,000 times.

Sector erase suspend mode allows system software to

suspend sector erase to read or write data from any other

sector.

Writing memory data is performed in word increments of

the device's 32K-word sectors typically within 0.8s and

4K-word sectors typically within 0.1s. Word program sus-

pend mode enables the system to read data or execute

code from any other memory array location.

M5M29GB640VP

features with individual sectors lock-

ing by using a combination of bits thirty-nine sector lock-

bits and WP, to lock and unlock sectors.

The status register indicates when the WSM's sector

erase, full chip erase, word program or lock configura-

tion operation is done.

The access time is 90/120ns (tELQV) over the operat-

ing temperature range (-40° to +80° and VCC supply

voltage range of 2.7V~3.6V.

M5M29GB640VP's

power saving mode feature substan-

P/N:PM0900

REV. 0.3, NOV. 21, 2002

M5M29GB640VP

BLOCK DIAGRAM

DQ0~DQ7

Output

Buffer

Input

Buffer

I/O

Logic

VCC

Output

Multiplexer

Identifier

Data

Status

Command

User

Interface

Data

Comparator

Write

State

Machine

A0~A21

Input

Buffer

Decoder

Y-Gating

Program/Erase

Voltage Switch

VPP

VCC

GND

Main Sector 29

Boot Sector 0

Boot Sector 1

Parameter Sector

Main Sector 30

Main Sector 0

Main Sector 1

Address

Latch

Decoder

32K-Word

Main Sector

x96

.......

Address

Counter

.......

P/N:PM0900

REV. 0.3, NOV. 21, 2002

M5M29GB640VP

Table 1. Pin Description

Symbol

A0-A21

Type

input

Description and Function

Address inputs for memory address. Data pin float to high-impedance when the chip is

deselected or outputs are disable. Addresses are internally latched during a write or

erase cycle.

Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-

gram command. Data is internally latched. Outputs array and configuration data. The

data pin float to tri-state when the chip is de-selected.

Activates the device's control logic, input buffers, and sense amplifiers. CE high de-

selects the memory device and reduce power consumption to standby level. CE is

active low.

Reset Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,

which drives the outputs to High Z, resets the WSM and minimizes current level.

When RP=VIH, the device is normal operation. When RP transition the device defaults

to the read array mode.

input

Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The

data and address is latched WE on the rising edge of the second WE pulse.

DQ0-DQ15

input/output

input

VCC

VCCQ

GND

supply

input

supply

Output enable: gates the device's outputs during a real cycle.

Write protect: when WP is VIL, the boot sectors cannot be written or erased. When WP

is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter

and main sectors.

Device power supply: (2.7V~3.6V).

I/O Power Supply: supplies for input/output buffers. (Refer to section 6.2.6)

Ground voltage: all the GND pin shall not be connected.

P/N:PM0900

REV. 0.3, NOV. 21, 2002

M5M29GB640VP

SECTOR STRUCTURE (TOP)

Sector

Boot Sector 0

Boot Sector 1

Parameter Sector 0

Parameter Sector 1

Parameter Sector 2

Parameter Sector 3

Parameter Sector 4

Parameter Sector 5

Main Sector 0

Main Sector 1

Main Sector 2

Main Sector 3

Main Sector 4

Main Sector 5

Main Sector 6

Main Sector 7

Main Sector 8

Main Sector 9

Main Sector 10

Main Sector 11

Main Sector 12

Main Sector 13

Main Sector 14

Main Sector 15

Main Sector 16

Main Sector 17

Main Sector 18

Main Sector 19

Main Sector 20

Main Sector 21

Main Sector 22

Main Sector 23

Main Sector 24

Main Sector 25

Main Sector 26

Main Sector 27

Main Sector 28

Main Sector 29

Main Sector 30

Sector Size

4K Word

32K Word

Address Range (h)

3FF000-3FFFFF

3FE000-3FEFFF

3FD000-3FDFFF

3FC000-3FCFFF

3FB000-3FBFFF

3FA000-3FAFFF

3F9000-3F9FFF

3F8000-3F8FFF

3F0000-3F7FFF

3E8000-3EFFFF

3E0000-3E7FFF

3D8000-3DFFFF

3D0000-3D7FFF

3C8000-3CFFFF

3C0000-3C7FFF

3B8000-3BFFFF

3B0000-3B7FFF

3A8000-3AFFFF

3A0000-3A7FFF

398000-39FFFF

390000-397FFF

388000-38FFFF

380000-387FFF

378000-37FFFF

370000-377FFF

368000-36FFFF

360000-367FFF

358000-35FFFF

350000-357FFF

348000-34FFFF

340000-347FFF

338000-33FFFF

330000-337FFF

328000-32FFFF

320000-327FFF

318000-31FFFF

310000-317FFF

308000-30FFFF

300000-307FFF

P/N:PM0900

REV. 0.3, NOV. 21, 2002