MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DESCRIPTION
The MITSUBISHI Mobile FLASH M5M29GB/T160BVP are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with
alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in
one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for
mobile and personal computing, and communication products. The M5M29GB/T160BVP are fabricated by CMOS technology for the
peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in in 48pin TSOP(I) .
FEATURES
Organization
.................................
1048,576 word x 16bit
.................................
2,097,152 word x 8 bit
Boot Block
M5M29GB160BVP
........................
Bottom Boot
M5M29GT160BVP
........................
Top Boot
Other Functions
Soft Ware Command Control
Selective Block Lock
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)
Package
48-Lead, 12mm x 20mm TSOP (type-I)
.............................
V
CC
= 2.7~3.6V
Supply voltage
................................
Access time
..............................
80ns (Vcc=3.3V+/-0.3V)
90ns (Vcc=2.7~3.6V)
Power Dissipation
.................................
54 mW (Max. at 5MHz)
Read
(After Automatic Power saving)
..........
0.33µW (typ.)
Program/Erase
.................................
126 mW (Max.)
.................................
0.33µW (typ.)
Standby
Deep power down mode
.......................
0.33µW (typ.)
Auto program for Bank(I)
.................................
4ms (typ.)
Program Time
Program Unit
.........................
1word/1byte
(Byte Program)
(Page Program)
.........................
128word/256byte
Auto program for Bank(II)
.................................
4ms (typ.)
Program Time
.................................
128word/256byte
Program Unit
Auto Erase
.................................
40 ms (typ.)
Erase time
Erase Unit
Bank(I) Boot Block
.....................
16Kword/32Kbyte x 1
..............
Parameter Block
16Kword/32Kbyte x 7
......................
32Kword/64Kbyte x 28
Bank(II) Main Block
Program/Erase cycles
APPLICATION
Code Strage
Digital Cellular Phone
Telecommunication
Mobile Computing Machine
PDA (Personal Digital Assistance)
Car Navigation System
Video Game Machine
.........................................
100Kcycles
PIN CONFIGURATION (TOP VIEW)
160BVP
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
NC
WE#
RP#
NC
WP#
RY/BY#
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
160BVP
A
16
BYTE#
GND
DQ
15
/A-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE#
GND
CE#
A
0
NC : NO CONNECTION
M5M29GB/T
160BVP
37
36
35
34
33
32
31
30
29
28
27
26
25
Outline 48pin TSOP type-I (12 X 20mm)
VP(Normal bend)
1
Mar 1999. Rev1.8
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
ADDRESS
INPUTS
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE#
OE#
WE#
WP#
RP#
BYTE#
RY/BY#
128 WORD PAGE BUFFER
Main Block
32KW
V
CC
(3.3V)
28
Bank(II)
GND (0V)
Main Block
Parameter Block7
Parameter Block6
Parameter Block5
Parameter Block4
Parameter Block3
Parameter Block2
Parameter Block1
Boot Block
X-DECODER
Bank(I)
32KW
16KW
16KW
16KW
16KW
16KW
16KW
16KW
16KW
Y-DECODER
Y-GATE / SENSE AMP.
STATUS / ID REGISTER
MULTIPLEXER
CHIP ENABLE INPUT
OUTPUT ENABLE INPUT
WRITE ENABLE INPUT
WRITE PROTECT INPUT
RESET/POWER DOWN INPUT
BYTE ENABLE INPUT
READY/BUSY OUTPUT
CUI
WSM
INPUT/OUTPUT
BUFFERS
DQ
15
/A
-1
DQ
14
DQ
13
DQ
12
DQ
3
DQ
2
DQ
1
DQ
0
DATA INPUTS/OUTPUTS
M5M29GB/T160BVP (8/16 bit version)
2
Mar 1999. Rev1.8
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FUNCTION
The M5M29GB/T160BVP includes on-chip program/erase control
circuitry. The Write State Machine (WSM) controls block erase
and byte/page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
A Deep Powerdown mode is enabled when the RP# pin is at GND,
minimizing power consumption.
Read
The M5M29GB/T160BVP has three read modes, which accesses
to the memory array, the Device Identifier and the Status Register.
The appropriate read command are required to be written to the
CUI. Upon initial device powerup or after exit from deep
powerdown, the M5M29GB/T160BVP automatically resets to read
array mode. In the read array mode, low level input to CE# and
OE#, high level input to WE# and RP#, and address signals to the
address inputs (A19-A-1:Byte Mode, A19-A0:Word Mode) output
the data of the addressed location to the data input/output
(D7-D0:Byte Mode, D15-D0:Word Mode).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while CE# is at low level and OE# is at
high level. Address and data are latched on the earlier rising edge
of WE# and CE#. Standard micro-processor write timings are
used.
Alternating Background Operation (BGO)
The M5M29GB/T160BVP allows to read array from one bank
while the other bank operates in software command write cycling
or the erasing / programming operation in the background. Read
array operation with the other bank in BGO is performed by
changing the bank address without any additional command.
When the bank address points the bank in software command
write cycling or the erasing / programming operation, the data is
read out from the status register. The access time with BGO is the
same as the normal read operation.
Output Disable
When OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.
Standby
When CE# is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
Deep Power-Down
When RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
Automatic Power-Saving (APS)
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or CE# isn't changed
more than 200ns after the last alternation. The power
consumption becomes the same as the stand-by mode. While
in this mode, the output data is latched and can be read out.
New data is read out correctly when addresses are changed.
3
Mar 1999. Rev1.8
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software
command into the Command User Interface.
Read Array Command
(FFH)
The device is in Read Array mode on initial device power up and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. After starting the internal operation the
device is set to the read status register mode automatically.
Read Device Identifier Command
(90H)
It can normally read device identifier codes when Read Device
Identifier Code Command(90H) is written to the command latch.
Following the command write, the manufacturer code and the
device code can be read from address 00000H and 00001H,
respectively.
Read Status Register Command
(70H)
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status
Register mode automatically.
The contents of Status Register are latched on the later falling
edge of OE# or CE#. So CE# or OE# must be toggled every status
read.
Clear Status Register Command
(50H)
The Erase Status, Program Status and Block Status bits are set to
"1"s by the Write State Machine and can only be reset by the Clear
Status Register command of 50H. These bits indicates various
failure conditions.
C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 256byte/128word can be loaded to the
page buffer by this two-command sequence. On the other hand,
all of the loaded data to the page buffer is programed
simultaneously by writing Page Buffer to Flash command of 0EH
followed by the confirm command of D0H. After completion of
programing the data on the page buffer is cleared automatically.
This command is valid for only Bank(I) alike Word/Byte Program.
Clear Page Buffer Command
(55H)
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.
Suspend/Resume Command
(B0H/D0H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The Bank
address is required when writing the Suspend/Resume Command.
The device continues to output Status Register data when read,
after the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the erase
operation or program operation has been suspended. At this
point, writing of the Read Array command to the CUI enables
reading data from blocks other than that which is suspended.
When the Resume command of D0H is written to the CUI,
the WSM will continue with the erase or program processes.
DATA PROTECTION
Block Erase / Confirm Command
(20H/D0H)
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Program Commands
A)Word/Byte Program (40H)
Word/Byte program is executed by a two-command sequence.
The Word/Byte Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word/Byte Program
Command is Valid for only Bank(I).
B)Page Program for Data Blocks (41H)
Page Program for Bank(I) and Bank(II) allows fast programming of
128words/256bytes of data. Writing of 41H initiates the page
program operation for the Data area. From 2nd cycle to 257th
cycle (Byte Mode)129th cycle (Word Mode), write data must be
serially inputted. Address A6-A0,A-1 (Byte Mode) / A6-A0 (Word
Mode) have to be incremented from 00H to 7FH/FFH. After
completion of data loading, the WSM controls the program pulse
application and verify operation.
The M5M29GB/T160BVP provides selectable block locking of
memory blocks. Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In addition, the
M5M29GB/T160BVP has a master Write Protect pin (WP#) which
prevents any modifications to memory blocks whose lock-bits are
set to "0", when WP# is low. When WP# is high, all blocks can be
programmed or erased regardless of the state of the lock-bits,
and the lock-bits are cleared to "1" by erase. See the BLOCK
LOCKING table on P.9 for details.
Power Supply Voltage
When the power supply voltage (Vcc) is less than V
LKO,
Low V
CC
Lock-Out voltage, the device is set to the Read-only mode.
Regarding DC electrical characteristics of V
LKO,
see P.10
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (2.7V).
During power up, RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
MEMORY ORGANIZATION
The M5M29GB/T160BVP has one 32Kbyte boot block, seven
32Kbyte parameter blocks, for Bank(I) and twenty-eight 64Kbyte
main blocks for Bank(II). A block is erased independently of other
blocks in the array.
4
Mar 1999. Rev1.8
MITSUBISHI LSIs
M5M29GB/T160BVP-80
16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Mitsubishi 16M Flash Memory Type name
M 5 M 29G T 160B VP
Operating Voltage :
29G : 2.7 - 3.6V
Standard / BGO Type
29W : 1.65 - 2.2V
Standard / BGO Type
Boot Block :
T : Top Boot
B : Bottom Boot
Density/Write Protect/
Word Organizetion:
160B : 16M WP#, x8/x16
161B : 16M WP1# & WP2#, x16
Package :
VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout)
WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm
5
Mar 1999. Rev1.8
