revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5408B is a family of 4-Mbit static RAMs organized as
524,288-words by 8-bit, fabricated by
Mitsubishi's high-
performance 0.25µm CMOS technology.
The M5M5408B is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic
TSOP and 32-pin 8mm x 13.4mm STSOP packages. Two types of
TSOPs and two types of STSOPs are available , M5M5408BTP
(normal-lead-bend TSOP) , M5M5408BRT (reverse-lead-bend
TSOP) , M5M5408BKV (normal-lead-bend STSOP) and
M5M5408BKR (reverse-lead-bend STSOP). These two types
TSOPs and two types STSOPs are suitable for a surface mounting
on double-sided printed circuit boards.
From the point of operating temperature, the family is divided
into three versions; "Standard", "W-version", and "I-version". Those
are summarized in the part name table below.
FEATURES
• Single +5V power supply
• Small stand-by current: 0.4µA(3V,typ.)
• No clocks, No refresh
• Data retention supply voltage=2.0V to 5.5V
• All inputs and outputs are TTL compatible.
• Easy memory expansion by S
• Common Data I/O
• Three-state outputs: OR-tie capability
• OE prevents data contention in the I/O bus
• Process technology: 0.25µm CMOS
• Package:
M5M5408BFP: 32 pin 525 mil SOP
M5M5408BTP/RT: 32 pin 400 mil TSOP(ll)
M5M5408BKV/KR: 32 pin 8mm x 13.4mm STSOP
PART NAME TABLE
Version,
Operating
temperature
Part name
(## stands for "FP","TP",
"RT","KV"or"KR")
M5M5408B## -55L
M5M5408B## -70L
5.0V
Power
Supply
Access
time
Stand-by current Icc
(PD)
, Vcc=3.0V
typical *
Ratings (max.)
25°C
---
70°C
50µA
85°C
---
max.
55ns
70ns
100ns
55ns
Active
current
Icc1
(5.0V, typ.)
Standard
0 ~ +70°C
M5M5408B## -10L
M5M5408B## -55H
M5M5408B## -70H
M5M5408B## -10H
M5M5408B## -55LW
M5M5408B## -70LW
5.0V
5.0V
70ns
100ns
55ns
70ns
100ns
55ns
0.4µA
10µA
---
---
---
100µA
50mA
(10MHz)
25mA
(1MHz)
W-
version
-20 ~ +85°C
M5M5408B## -10LW
M5M5408B## -55HW
M5M5408B## -70HW
M5M5408B## -10HW
M5M5408B## -55LI
M5M5408B## -70LI
5.0V
5.0V
70ns
100ns
55ns
70ns
100ns
55ns
0.4µA
---
20µA
---
---
100µA
I-
version
-40 ~ +85°C
M5M5408B## -10LI
M5M5408B## -55HI
M5M5408B## -70HI
M5M5408B## -10HI
5.0V
70ns
100ns
0.4µA
---
20µA
* "typical" parameter is sampled, not 100% tested.
MITSUBISHI ELECTRIC
1
revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
PIN CONFIGURATION (TOP VIEW)
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
(0V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
(5V)
A
15
A
17
W
A
13
A
8
A
9
A
11
OE
A
10
S
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
(5V)
V
CC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
15
A
17
W
A
13
A
8
A
9
A
11
OE
A
10
S
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
A
18
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
GND
(0V)
Outline
32P2M-A (FP)
32P3Y-H (TP)
Outline
32P3Y-J (RT)
A
11
A
9
A
8
A
13
W
A
18
A
15
Vcc
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
M5M5408BKV
OE
A
10
S
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
Vcc
A
15
A
18
W
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
M5M5408BKR
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
DQ1
DQ2
DQ3
GND
DQ4
DQ5
DQ6
DQ7
DQ8
S
A
10
OE
Outline
32P3K-B
Outline
32P3K-C
MITSUBISHI ELECTRIC
2
revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The M5M5408BFP,TP,RT,KV,KR is organized as 524,288-
words by 8-bit. These devices operate on a single +5.0V
power supply, and are directly TTL compatible to both input
and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
A write operation is executed during the S low and W low
overlap time. The address(A0~A18) must be set up before
the write cycle
A read operation is executed by setting W at a high level
and OE at a low level while S are in an active state(S=L).
When setting S at a high level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-impedance
state, allowing OR-tie with other chips. Setting the OE at a high
level,the output stage is in a high-impedance state, and the
data bus contention problem in the write cycle is eliminated.
The power supply current is reduced as low as 0.4µA(25°C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure
or power-down operation in the non-selected mode.
FUNCTION TABLE
S
H
L
L
L
W
X
L
H
H
OE
X
X
L
H
Mode
Non selection
Write
Read
Read
DQ
High-impedance
Data input (D)
Data output (Q)
High-impedance
Icc
Standby
Active
Active
Active
Pin
A0 ~ A18
S
W
OE
Vcc
GND
Function
Address input
Chip select input
Write control input
Output inable input
Power supply
Ground supply
DQ1 ~ DQ8 Data input / output
BLOCK DIAGRAM
M5M5408B
FP/TP/RT
M5M5408BKV/KR
16
15
14
13
12
11
10
9
6
7
21
22
M5M5408BKV/KR
A
4
A
5
A
6
A
7
A
12
A
14
A
16
A
17
A
18
A
15
A
10
A
11
A
9
A
8
A
13
8
7
6
5
4
3
2
30
1
31
M5M5408B
FP/TP/RT
13
14
15
17
18
19
20
21
MEMORY ARRAY
524288 WORDS
x 8 BITS
23
25
26
27
28
29
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
23
25
26
27
28
31
1
2
3
4
5
30
32
29
22
24
CLOCK
GENERATOR
W
S
OE
V
CC
(3V)
A
0
A
1
A
2
A
3
12
11
10
9
20
19
18
17
8
32
24
16
GND
(0V)
MITSUBISHI ELECTRIC
3
revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
temperature
Storage temperature
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Standard
(-L, -H)
(-LW, -HW)
(-LI, -HI)
W-version
I-version
Ratings
Units
Vcc
V
I
V
O
P
d
T
a
T
stg
-0.3
*
~ +7
-0.3
*
~ Vcc + 0.3
0 ~ Vcc
700
0 ~ +70
-20 ~ +85
-40 ~ +85
-65 ~150
V
mW
°C
°C
* -3.0V in case of AC (Pulse width
≤
30ns)
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
I
OH
= -1mA
High-level output voltage 2
I
OH
= -0.1mA
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
( AC,MOS level )
Active supply current
( AC,TTL level )
Stand by supply current
( AC,MOS level )
Conditions
( Vcc=5V±10%, unless otherwise noted)
Limits
Min
Typ
Max
Vcc+0.3V
Units
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
Icc
1
Icc
2
2.2
-0.3 *
2.4
Vcc-0.5V
0.8
V
0.4
±1
±1
I
OL
=2mA
V
I
=0
~
Vcc
S=V
IH
or OE=V
IH,
V
I/O
=0
~
Vcc
S
≤0.2V
Output-open
Other inputs
≤0.2V
or
≥Vcc-0.2V
Output-open
S=VIL
Other inputs=V
IH
or V
IL
S
≥Vcc-0.2V
Other inputs=0~Vcc
minimum cycle
µA
f= 1MHz
minimum cycle
-
-
-
-
-
-
-
-
-
f= 1MHz
-LW, -LI
-L
-HW, -HI
-H
Icc
3
50
25
60
30
-
-
0.4
0.4
-
80
30
90
40
200
100
40
20
3
mA
µA
Icc
4
Stand by supply current
( AC,TTL level )
S=V ,Other inputs= 0 ~ Vcc
mA
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=5.0V and Ta=25°C
* -3.0V in case of AC (Pulse width
≤
50ns)
CAPACITANCE
Symbol
Parameter
Input capacitance
Output capacitance
Conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=
GND,V
O
=25mVrms, f=1MHz
(Vcc=5.0V±10%, unless otherwise noted)
Limits
Typ
Max
Units
Min
C
I
C
O
8
10
pF
MITSUBISHI ELECTRIC
4
revision-K0.1e, ' 98.07.30
MITSUBISHI LSIs
M5M5408BFP/TP/RT/KV/KR
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply voltage
Input pulse
Input rise time and fall time
Reference level
5.0V
(Vcc=5.0V±10%, unless otherwise noted)
VIH=2.4V,VIL=0.6V
(FP,TP,RT,KV,KR-70,-10 )
VIH=3.0V,VIL=0V
(FP,TP,RT,KV,KR-55 )
5ns
VOH=VOL=1.5V
Transition is measured ±500mV from
steady state voltage.
(for ten,tdis)
Fig.1, CL=100pF
(FP,TP,RT,KV,KR-70,-10 )
CL=30pF
(FP,TP,RT,KV,KR-55 )
CL=5pF
(for ten,tdis)
1.8kΩ
DQ
990Ω
CL
Output loads
CL Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
Parameter
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after S high
Output disable time after OE high
Output enable time after S low
Output enable time after OE low
Data valid time after address
M5M5408BFP,TP,RT,
KV,KR-55
M5M5408BFP,TP,RT, M5M5408BFP,TP,RT,
KV,KR-70
KV,KR-10
Units
Min
Max
Min
Max
Min
Max
t
CR
t
a
(A)
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
55
55
55
25
20
20
10
5
10
70
70
70
35
25
25
10
5
10
100
100
100
50
35
35
10
5
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
Symbol
Parameter
Write cycle time
Write pulse width
Address set up time
Address set up time with respect to W high
Chip select set up time
Data set up time
Data hold time
Write recovery time
Output disable time after W low
Output disable time after OE high
Output enable time after W high
Output enable time after OE low
M5M5408BFP,TP,RT,
KV,KR-55
M5M5408BFP,TP,RT, M5M5408BFP,TP,RT,
KV,KR-10
KV,KR-70
Units
Min
Max
Min
Max
Min
Max
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
55
40
0
50
50
25
0
0
20
20
5
5
70
50
0
60
60
30
0
0
25
25
5
5
100
60
0
80
80
35
0
0
35
35
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI ELECTRIC
5
