M62320P/FP
8-bit I/O Expander for I
2
C BUS
REJ03D0863-0300
Rev.3.00
Mar 25, 2008
Description
The M62320P/FP is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial data converting
functions.
It can communicate with a microcontroller via few wiring thanks to the adoption of the two-line I
2
C BUS.
Parallel data I/O terminal can be set to input or output mode alternatively in individual bits.
Maximum 8 ICs can be connected to a bus by using three chip-select pins, so that it is possible to handle up to 64 bits
data.
Features
•
Simple two-line (SCL and SDA) communication with a microcontroller.
•
8-bit data conversion between serial and parallel by I
2
C BUS.
•
Built-in power-on reset.
Application
I/O port expansion for a microcontroller.
Data conversion between serial and parallel in microcontroller peripherals.
Block Diagram
CS0
16
CS1
15
Chip-select
SCL
2
CS2
14
SDA 3
I
2
C Bus
transceiver
Output data
8
Output data
latch
8
Shift register
Input/output
8
1 SO
8
Input data
latch
8
Input data
I/O setting
data latch
8
V
DD
13
GND 8
Power-on
reset
I/O port
12
D7
11
D6
10
D5
9
D4
7
D3
6
D2
5
D1
4
D0
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 1 of 10
M62320P/FP
Pin Arrangement
M62320P/FP
SO
SCL
SDA
D0
D1
D2
D3
GND
1
2
3
4
5
6
7
8
(Top view)
Outline: PRDP0016AA-A (16P4)
PRSP0016DE-A (16P2N-A)
16 CS0
15 CS1
14 CS2
13 V
DD
12 D7
11 D6
10 D5
9
D4
Pin Description
Pin No.
2
3
1
16
15
14
4
5
6
7
9
10
11
12
13
8
Pin Name
SCL
SDA
SO
CS0
CS1
CS2
D0
D1
D2
D3
D4
D5
D6
D7
V
DD
GND
I/O
Input
Input/Output
Output
Input
Serial clock input
Serial data input/output
Serial data output
Chip select data input
Function
Input/Output
Parallel data input/output
—
—
Power supply
GND
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 2 of 10
M62320P/FP
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Output current "Low"
Output current "High"
Power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
V
l
V
O
I
OH
I
OL
Pd
Topr
Tstg
Ratings
–0.3 to +7.0
–0.3 to V
DD
+ 0.3
–0.3 to V
DD
+ 0.3
–5 to 0
0 to 30
1220 (P) / 980 (FP)
–20 to +85
–40 to +125
Unit
V
V
V
mA
mA
mW
°C
°C
Conditions
D0 to D7
D0 to D7
Ta = 25°C
Recommended Operating Conditions
•
Supply voltage:
•
Input high voltage:
•
Input low voltage:
V
DD
= 3V to 5.5 V
V
IH
= 0.7 V
DD
to V
DD
V
IL
= 0 to 0.2 V
DD
Electrical Characteristics
(V
DD
= 5 V
±
10%, GND = 0 V, Ta = –20 to +85°C, unless otherwise noted)
Item
Circuit current
Symbol
I
DD
Min
—
—
Input leak current
Output low voltage
(SDA)
Input high voltage
Input low voltage
Output high voltage
(D0 to D7)
Output low voltage
(D0 to D7)
Output current "Low"
(D0 to D7)
I
ILK
V
OL
V
IH
V
IL
V
OH
V
OL
I
OL
–10
—
0.7 V
DD
—
V
DD
– 0.4
V
DD
– 0.4
0
0
5
2.5
15
5
Limits
Typ
0.05
0.1
—
—
—
—
—
—
—
—
10
5
25
10
Max
0.5
1.0
10
0.4
—
0.2 V
DD
V
DD
V
DD
0.4
0.4
—
—
—
—
Unit
mA
µA
µA
V
V
V
V
V
mA
Conditions
V
IH
= V
DD
, V
IL
= GND,
f
SCL
= 400 kHz
V
IH
= V
DD
, V
IL
= GND,
f
SCL
= stop
Isink = 3 mA
I
OH
=–1 mA, V
DD
= 5 V
I
OH
= –500
µA,
V
DD
= 3 V
I
OL
= 5 mA, V
DD
= 5 V
I
OL
= 2.5 mA, V
DD
= 3 V
V
OL
= 0.4V, V
DD
= 5 V
V
OL
= 0.4 V, V
DD
= 3 V
V
OL
= 1.0 V, V
DD
= 5 V
V
OL
= 1.0 V, V
DD
= 3 V
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 3 of 10
M62320P/FP
I
2
C BUS Characteristics
Limits
Item
SCL clock frequency
Free time: the bus must be free before a new transmission can start
Hold time START Condition
After this period, the first clock pulse is generated.
Low period of the clock
High period of the clock
Set-up time for START condition
Only relevant for a repeated START condition
Data Hold time
Data Set-up time
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
Note:
Symbol
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
Min
0
4.7
4.0
4.7
4.0
4.7
0
250
—
—
4.0
Max
100
—
—
—
—
—
—
—
1000
300
—
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Timing Chart
t
R
, t
F
t
BUF
V
IH
SDA
V
IL
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STA
t
SU:STO
V
IH
SCL
V
IL
t
LOW
t
HIGH
Start
Start
Stop
Start
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 4 of 10
M62320P/FP
Functional Blocks
I
2
C BUS Interface
The I
2
C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection by receiving
SDA, SCL, CS0, CS1 and CS2 signals and then the latch pulses, dedicated to each data latch are generated.
Data Latch
This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch and each latch
is controlled by the I
2
C BUS interface.
•
I/O setting data latch
These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next byte after
receiving the slave address byte in the write mode from the master. In case this latch is set to high, the data is
transferred from the I
2
C BUS interface to the parallel data terminals. In the opposite transmission: from the parallel
data terminals to the I
2
C BUS, it is set to low.
•
Output data latch
In the write mode, the data from the I
2
C BUS to the parallel data terminals is latched. When the master transmits
output data after a setting in write mode, the output data is taken into the latches.
•
Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is taken into
the latches from the parallel data terminals on every 8th negative edge of SCL clock. The latched data is output to
the master through the sift resistor. On the output terminal assigned by the I/O setting latch, the input data latch
takes the state of the output terminal.
Parallel Input/Output Port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and is able to
accept an input. In another case I/O setting latch is set to high (output mode), each parallel terminal output a data
according to the state of the output data latch.
Power on Reset
When power is turned on, each latch is reset and then the parallel data I/O terminals become hi-impedance (input mode).
REJ03D0863-0300 Rev.3.00 Mar 25, 2008
Page 5 of 10
stm32/stm8
