M66591GP
ASSP (USB2.0 Peripheral Controller)
REJ03F0101-0100Z
Rev.1.00
Nov. 30, 2004
1
Overview
1.1 Overview
The M66591 is a general-purpose USB (Universal Serial Bus) device controller compliant with the Universal Serial
Bus Specification Revision 2.0 and supports both Hi-Speed and Full-Speed transfer.
The USB Hi-Speed and Full-Speed transceiver are built-in, and the M66591 meets control, bulk and interrupt
transfer types which are defined in the Universal Serial Bus Specification Revision 2.0.
The M66591 has a 3.5K byte FIFO and 7 endpoints (maximum) for data transfer.
Further, being equipped with the split bus (DMA interface) which is independent from the CPU bus interface, the
M66591 is suitable for use in systems that require large capacity data transfer at Hi-Speed.
1.2 Features
♦
♦
♦
♦
Universal Serial Bus Specification Revision 2.0 compliant
Built-in USB transceiver
Supports both Hi-Speed (480M bps) and Full-Speed (12M bps)
USB protocol layer by hardware
•
Bit stuffing encoding and decoding
•
CRC (Cyclic Redundancy Check) generation and checking
•
NRZI (Non Return Zero Invert) encoding and decoding
•
Packet detection
•
USB address checking
Hi-Speed and Full-Speed detection by hardware
Supports the following USB transfer types
•
Control transfer (PIPE0)
•
Bulk transfer (PIPE1~PIPE4)
•
Interrupt transfer (PIPE5~PIPE6)
Built-in FIFO buffer (3.5K bytes) for endpoints
Up to 7 endpoints selectable
Data transfer condition selectable for each PIPE
•
Hi-Speed
- PIPE0: Control transfer, continuous transfer mode, 256-byte FIFO
- PIPE1~2: Bulk in or bulk out transfer, 512-byte FIFO, double buffer
- PIPE3~4: Bulk in or bulk out transfer, 512-byte FIFO, single buffer
- PIPE5~6: Interrupt in transfer, 64-byte FIFO, single buffer
•
Full-Speed
- PIPE0: Control transfer, continuous transfer mode, 256-byte FIFO
- PIPE1~2: Bulk in or bulk out transfer, continuous transfer mode, 512-byte FIFO, double buffer
- PIPE3~4: Bulk in or bulk out transfer, continuous transfer mode, 512-byte FIFO, single buffer
- PIPE5~6: Interrupt in transfer, 64-byte FIFO, single buffer
Automatic response for Set Address request
Supports the following input frequency
•
12 / 24 / 48MHz
Supports 16-bit CPU I/F and 8/16-bit DMA transfer
Supports separate/multiplex bus
•
16-bit separate/multiplex bus
Supports 8-bit split bus (DMA interface)
USB status output for power management
1.8V/3.3V interface power supply
Application
•
Digital camera, printer, external storage device and all Hi-Speed USB PC peripheral device
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Rev.1.00 Nov. 30, 2004 page 1 of 131
M66591GP
1.3 Pin Configuration
The pin configuration (top view) of the M66591 is shown in Figure 1.1.
DGND(GND)
DGND(GND)
SD0/PA0
D7/AD7
D6/AD6
D5/AD5
D4/AD4
D3/AD3
D2/AD2
42
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
SD1/PA1
SD2/PA2
SD3/PA3
SD4/PA4
SD5/PA5
SD6/PA6
SD7/PA7
INT
RD_N
WR0_N
WR1_N
CS_N
VDD
DGND(GND)
DREQ
DACK
DSTB_N
DEND
RST_N
VIF
41
D1/AD1
VDD
D15
D14
D13
D12
D10
D11
VIF
D9
D8
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
10
12
13
14
15
16
17
18
19
20
11
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
D0
A7/ALE
A6
A5
A4
A3
A2
A1
SUSP_ON
CONF_ON
VDD
DGND(GND)
VIF
MPBUS
TEST1
TEST0
XOUT
XIN
DGND(GND)
VDD
M66591GP
(Top View)
31
30
29
28
27
26
25
24
23
22
21
DFP
AFEDGND
AFEAVDD
AFEAVDD
AFEAVDD
BIASGND
DGND(GND)
AFEAGND
AFEAGND
REFRIN
VBUS
DHP
TR_ON
RPU
BIASVDD
AFEDVDD
PLLGND
M66591GP: 80pin LQFP (0.4mm pitch, Outline: 80P6R-A)
Figure 1.1 Pin Configuration of M66591
Rev.1.00 Nov. 30, 2004 page 2 of 131
PLLVDD
DFM
DHM
M66591GP
The pin functions of the M66591 are shown in Table 1.1.
Table 1.1 Pin Functions of M66591
Item
CPU
interface
D7/AD7-D1/AD
1, D0
Input/Output
Pin Name
D15-D8
Input/Output
Input/Output
Name / Function
Data Bus
These are data bus to access the registers from the CPU.
Data Bus / Address Bus
When select to 16-bit separate bus, these pins are used as D7-D0 of data bus.
When select to 16-bit multiplex bus, D7-D0 input/output and AD7-AD1 input are
performed at time-sharing. In this case, AD0 is not used.
A7/ALE, A6-A1
Input
Address Bus / Address Latch Enable
When select to 16-bit separate bus, these pins are address bus to access the
registers from the CPU.
When select to 16-bit multiplex bus, A7 becomes the ALE pin, latching addresses
at the falling edge. A6-A1 are not used.
CS_N
RD_N
WR1_N
WR0_N
MPBUS
Input
Input
Input
Input
Input
Chip Select
When this pin is low level, M66591 is selected.
Read Strobe
Data are read from registers at low level.
D15-D8 Byte Write Strobe
The data (D15-D8) are written to the registers at the rising edge.
D7-0 Byte Write Strobe
The data (D7-D0) are written to the registers at the rising edge.
Bus Mode Select
The 16-bit separate bus is selected at low level.
The 16-bit multiplex bus is selected at high level.
This pin should not be switched after H/W reset.
Interrupt
interface
INT
Output
Interrupt
Interrupts are requested to the CPU. Polarity of this pin can be selected by register
setting.
DMA
interface
SD7/PA7-SD0/
PA0
DREQ
Output
Input/Output
Split Bus / General-purpose Port
These pins are used to select either split bus (DMA Interface) or general-purpose
port (GPIO).
DMA Request
This pin is used to request DMA transfer of the D0_FIFO port. Polarity of this pin
can be selected by register setting.
DACK
Input
DMA Acknowledge
DMA transfer of the D0_FIFO port is enabled in either low or high level. Polarity of
this pin can be selected by register setting.
DSTB_N
Input
Split Bus Strobe
This pin is used as data strobe signal when the D0_FIFO port has been set to the
split bus (DMA Interface).
When the RWstb bit of the Data Pin & FIFO/DMA Control Pin Configuration
Register 2 is set to “1” (RD/WR strobe mode), this pin is used as data strobe signal.
DEND
Input/Output
Transfer Terminal
When the PIPE direction is “IN”, this pin receives transfer complete signal as an
input signal from any other peripheral chip or the CPU.
When the PIPE direction is “OUT”, this pin indicates the last data transferred as the
output signal. Polarity of this pin can be set by a register.
USB
interface
DHM
DFP
DFM
Input/Output
Input/Output
Input/Output
DHP
Input/Output
USB Hi-Speed Data
Connect the D+ signal of USB bus.
USB Hi-Speed Data
Connect the D- signal of USB bus.
USB Full-Speed Data
Connect this pin to DHP via a 43Ω 1% resistance.
USB Full-Speed Data
Connect this pin to DHM via a 43Ω 1% resistance.
1
1
1
1
1
1
1
1
8
1
1
1
1
1
1
7
8
Pin
Count
8
Rev.1.00 Nov. 30, 2004 page 3 of 131
M66591GP
Pin
Count
1
1
Item
Pin Name
RPU
TR_ON
Input/Output
Input
Output
Name / Function
Pull-up Control
Connect this pin to TR_ON pin via a 1.5KΩ 5% resistance.
Pull-up Power Supply Output
3.3V power supply output for pull-up. This supply internally converts VBUS input
from 5V to 3.3V and outputs it.
VBUS
Input
VBUS Input
Connect to the Vbus of USB bus. Connection or shutdown of the Vbus can be
detected.
1
REFRIN
USB status
output
SUSP_ON
CONF_ON
Input
Output
Reference Input
Connect this pin to BIASGND via a 1.2KΩ 1% resistance.
USB Configured Output
This pin is used to indicate the transition to configured state. This pin is N-ch open
drain output.
1
1
Output
USB Suspend Output
This pin is used to indicate the transition to suspend state. This pin is N-ch open
drain output.
1
Clock
XIN
XOUT
Input
Output
Input
Oscillator
Input
Oscillator
Output
Reset
These pins are used to input/output the signals of internal clock
oscillation circuits. Connect a crystal unit between Xin and Xout pins.
If an external clock signal is used, input it to the Xin pin. Leave Xout
open.
1
1
1
System
control
RST_N
This pin is used to initialize the values of the internal register or the counter at low
level.
TEST1-0
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Test
These pins are input for the test. Fix to low level or keep open.
Analog Power Supply
Connect to the 3.3V power supply.
AFEAGND
AFEDVDD
AFEDGND
BIASVDD
BIASGND
PLLVDD
PLLGND
VDD
VIF
DGND
Analog Ground
USB Transceiver Digital Power Supply
Connect to the 3.3V power supply.
USB Transceiver Digital Power Ground
BIAS Power Supply
Connect to the 3.3V power supply.
BIASGND
PLL Power Supply
Connect to the 3.3V power supply.
PLLGND
Core Power Supply
Connect to the 3.3V power supply.
IO Power Supply
Connect to the 1.8V or 3.3V power supply.
Digital Ground
6
3
1
4
1
1
1
1
2
1
2
3
Power
supply
AFEAVDD
The care method of non-used pin of M66591are shown in Table 1.2.
Table 1.2 The care method of non-used pin of M66591
Item
CPU interface
DMA interface
A6-A1
SD7/PA7-SD0/PA0
DREQ
DACK, DEND
DSTB_N
System control
USB status output
TEST1-0
CONF_ON, SUSP_ON
Pin Name
Open
Pull-up or pull-down or setting to output port
Open
Pull-up or pull-down or connect to VIF
Pull-up or connect to VIF
Open or connect to GND
Open
Care Method
Rev.1.00 Nov. 30, 2004 page 4 of 131
M66591GP
1.4 Pin Functions
The pin functions of the M66591are shown in Figure 1.2.
DMA
Interface
DREQ
DACK
DSTB_N
DEND
XIN
XOUT
Clock
CPU
Interface
D15-D8
D7/AD7-D1/AD1, D0
SD7/PA7-SD0/PA0
A7/ALE, A6-A1
CS_N
RD_N
WR0_N
WR1_N
MPBUS
8
8
8
7
M66591
VBUS
TR_ON
RPU
DHP
DHM
DFP
DFM
REFRIN
USB
Interface
INT
RST
TEST0
TEST1
Interrupt
System
Control
CONF_ON
SUSP_ON
USB Status
Output
Figure 1.2 Pin Function Diagram of M66591
Rev.1.00 Nov. 30, 2004 page 5 of 131
