Reference Guide
M68HC11ERG/AD
Rev. 2, 10/2003
M68HC11E Series
Programming
Reference Guide
Block Diagram
MODA/ MODB/
LIR
V
STBY
XTAL EXTAL
E
IRQ
XIRQ/V
PPE*
RESET
OSC
MODE CONTROL
CLOCK LOGIC
PULSE ACCUMULATOR
COP
PAI
OC2
OC3
OC4
OC5/IC4/OC1
IC1
IC2
PERIODIC INTERRUPT
IC3
INTERRUPT
LOGIC
ROM OR EPROM
(SEE TABLE)
TIMER
SYSTEM
M68HC11 CPU
EEPROM
(SEE TABLE)
RAM
(SEE TABLE)
R/W
AS
BUS EXPANSION
ADDRESS
ADDRESS/DATA
SERIAL
PERIPHERAL
INTERFACE
SPI
SERIAL
COMMUNICATION
INTERFACE
SCI
V
DD
V
SS
STRB
STRA
SS
SCK
MOSI
MISO
TxD
RxD
STROBE AND HANDSHAKE
PARALLEL I/O
V
RH
V
RL
A/D CONVERTER
CONTROL
PORT A
PORT B
PORT C
CONTROL
PORT D
PORT E
STRB/R/W
PA7/PAI
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/IC4/OC1
PA2/IC1
PA1/IC2
PA0/IC3
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TxD
PD0/RxD
STRA/AS
PB7/ADDR15
PB6/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11
PB2/ADDR10
PB1/ADDR9
PB0/ADDR8
PC7/ADDR7/DATA7
PC6/ADDR6/DATA6
PC5/ADDR5/DATA5
PC4/ADDR4/DATA4
PC3/ADDR3/DATA3
PC2/ADDR2/DATA2
PC1/ADDR1/DATA1
PC0/ADDR0/DATA0
* V
PPE
applies only to devices with EPROM/OTPROM.
DEVICE
MC68HC11E0
MC68HC11E1
MC68HC11E9
MC68HC711E9
MC68HC11E20
MC68HC711E20
MC68HC811E2
RAM
512
512
512
512
768
768
256
ROM
—
—
12 K
—
20 K
—
—
PE7/AN7
PE6/AN6
PE5/AN5
PE4/AN4
PE3/AN3
PE2/AN2
PE1/AN1
PE0/AN0
EPROM
—
—
—
12 K
—
20 K
—
EEPROM
—
512
512
512
512
512
2048
© Motorola, Inc., 2003
M68HC11ERG/AD
Devices Covered in This Reference Guide
Device
MC68HC11E0
MC68HC11E1
MC68HC11E9
MC68HC711E9
MC68HC11E20
MC68HC711E20
MC68HC811E2
RAM
512
512
512
512
768
768
256
ROM
—
—
12K
—
20K
—
—
EPROM
—
—
—
12K
—
10K
—
EEPROM
—
512
512
512
512
512
2048
M68HC11E Series Programming Model
7
15
A
0
D
IX
IY
SP
PC
7
B
0
0
8-BIT ACCUMULATORS A & B
OR 16-BIT DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
7
S
0
X
H
I
N
Z
V
C
CONDITION CODES
CARRY/BORROW FROM MSB
OVERFLOW
ZERO
NEGATIVE
I-INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X-INTERRUPT MASK
STOP DISABLE
2
M68HC11E Series Programming Reference Guide
MOTOROLA
M68HC11ERG/AD
Crystal Dependent Timer Summary
Crystal Dependent Timer Summary
Selected
Crystal
CPU Clock
Cycle Time
(E)
(1/E)
Common XTAL Frequencies
4.0 MHz
1.0 MHz
1000 ns
8.0 MHz
2.0 MHz
500 ns
12.0 MHz
3.0 MHz
333 ns
Pulse Accumulator (in Gated Mode)
(E/2
6
)
(E/2
14
)
1 count —
overflow —
PR[1:0]
(E/1)
(E/2
16
)
(E/4)
(E/2
18
)
(E/8)
(E/2
19
)
(E/16)
(E/2
20
)
00
1 count—
overflow —
01
1 count—
overflow —
10
1 count—
overflow —
11
1 count—
overflow —
RTR[1:0]
(E/2
13
)
(E/2
14
)
(E/2
15
)
(E/2
16
)
00
01
10
11
CR[1:0]
(E/2
15
)
(E/2
17
)
(E/2
19
)
(E/2
21
)
00
01
10
11
Timeout
tolerance
(–0 ms/+...)
1.0
µs
65.536 ms
4.0
µs
262.14 ms
8.0
µs
524.29 ms
16.0
µs
1.049 s
64.0
µs
16.384 ms
32.0
µs
8.192 ms
Main Timer Count Rates
500 ns
32.768 ms
2.0
µs
131.07 ms
4.0
µs
262.14 ms
8.0
µs
524.29 ms
333 ns
21.845 ms
1.333
µs
87.381 ms
2.667
µs
174.76 ms
5.333
µs
349.52 ms
21.330
µs
5.491 ms
Periodic (RTI) Interrupt Rates
8.192 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
2.731 ms
5.461 ms
10.923 ms
21.845 ms
COP Watchdog Timeout Rates
32.768 ms
131.072 ms
524.288 ms
2.097 s
16.384 ms
65.536 ms
262.14 ms
1.049 s
10.923 ms
43.691 ms
174.76 ms
699.05 ms
(E/2
15
)
32.8 ms
16.4 ms
10.9 ms
MOTOROLA
M68HC11E Series Programming Reference Guide
3
M68HC11ERG/AD
Interrupt Vector Assignments
Vector
Address
FFC0, C1 – FFD4, D5 Reserved
SCI serial system
(1)
• SCI receive data register full
• SCI receiver overrun
• SCI transmit data register empty
• SCI transmit complete
• SCI idle line detect
SPI serial transfer complete
Pulse accumulator input edge
Pulse accumulator overflow
Timer overflow
Timer input capture 4/output compare 5
Timer output compare 4
Timer output compare 3
Timer output compare 2
Timer output compare 1
Timer input capture 3
Timer input capture 2
Timer input capture 1
Real-time interrupt
IRQ (external pin)
XIRQ pin
Software interrupt
Illegal opcode trap
COP failure
Clock monitor fail
RESET
Interrupt
Source
CCR
Mask Bit
—
Local
Mask
—
RIE
RIE
TIE
TCIE
ILIE
SPIE
PAII
PAOVI
TOI
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
IC2I
IC1I
RTII
None
None
None
None
NOCOP
CME
None
FFD6, D7
I
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
I
I
I
I
I
I
I
I
I
I
I
I
I
I
X
None
None
None
None
None
1. Interrupts generated by SCI; read SCSR to determine source. Refer to HPRIO register to
determine priority of interrupt.
4
M68HC11E Series Programming Reference Guide
MOTOROLA
M68HC11ERG/AD
M68HC11E Series Memory Maps
M68HC11E Series Memory Maps
$0000
EXT
$1000
EXT
0000
512 BYTES RAM
01FF
1000
103F
64-BYTE REGISTER BLOCK
$B600
EXT
EXT
BF00
BFFF
$D000
BOOT
ROM
BFC0
BFFF
SPECIAL MODES
INTERRUPT
VECTORS
FFC0
$FFFF
EXPANDED
BOOTSTRAP
SPECIAL
TEST
FFFF
NORMAL
MODES
INTERRUPT
VECTORS
Figure 1. Memory Map for MC68HC11E0
$0000
EXT
$1000
EXT
EXT
EXT
0000
512 BYTES RAM
01FF
1000
103F
64-BYTE REGISTER BLOCK
B600
$B600
EXT
EXT
BFFF
$D000
FFC0
FFFF
EXPANDED
BOOTSTRAP
SPECIAL
TEST
B7FF
BF00
512 BYTES EEPROM
BOOT
ROM
BFC0
BFFF
SPECIAL MODES
INTERRUPT
VECTORS
$FFFF
NORMAL
MODES
INTERRUPT
VECTORS
Figure 2. Memory Map for MC68HC11E1
MOTOROLA
M68HC11E Series Programming Reference Guide
5
