M95040
M95020, M95010
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
s
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
s
Figure 1. Packages
Single Supply Voltage:
– 4.5V to 5.5V for M950x0
– 2.5V to 5.5V for M950x0-W
– 1.8V to 3.6V for M950x0-S
s
s
s
s
s
s
s
s
5 MHz Clock Rate (maximum)
Status Register
BYTE and PAGE WRITE (up to 16 Bytes)
Self-Timed Programming Cycle
Adjustable Size Read-Only EEPROM Area
Enhanced ESD Protection
More than 1,000,000 Erase/Write Cycles
More than 40 Year Data Retention
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
July 2003
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M95040, M95020, M95010
SUMMARY DESCRIPTION
The M95040 is a 4 Kbit (512 x 8) electrically eras-
able programmable memory (EEPROM), access-
ed by a high speed SPI-compatible bus. The other
members of the family (M95020, M95010) are
identical, though proportionally smaller (2 and 1
Kbit, respectively).
Each device is accessed by a simple serial
interface that is SPI-compatible. The bus signals
are C, D and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD). WRITE instruc-
tions are disabled by Write Protect (W).
Figure 2. Logic Diagram
Note: 1. See page 28 (onwards) for package dimensions, and how
to identify pin-1.
Figure 3. DIP, SO and TSSOP Connections
M95xxx
S
Q
W
VSS
1
2
3
4
8
7
6
5
AI01790D
VCC
HOLD
C
D
VCC
Table 1. Signal Names
D
C
S
W
HOLD
M95xxx
Q
C
D
Q
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
S
W
HOLD
V
CC
VSS
AI01789C
V
SS
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M95040, M95020, M95010
SIGNAL DESCRIPTION
V
CC
must be held within the specified range:
V
CC
(min) to V
CC
(max).
All of the input and output signals can be held High
or Low (according to voltages of V
IH
, V
OH
, V
IL
or
V
OL
, as specified in Tables 12 to 16). These sig-
nals are described next.
Serial Data Output (Q)
This output signal is used to transfer data serially
out of the device. Data bytes are shifted out on the
falling edge of the Serial Clock (C).
Serial Data Input (D)
This input signal is used to transfer data serially
into the device. Instructions, addresses, and input
data bytes are shifted in on the rising edge of the
Serial Clock (C).
Serial Clock (C)
This input signal provides the timing for the serial
interface.
Chip Select (S)
When this input signal is High, the device is dese-
lected, and the Serial Data Output (Q) is high im-
pedance.
Hold (HOLD)
This input signal is used to pause temporarily any
serial communications with the device, without los-
ing bits that have already been passed on the se-
rial bus.
Write Protect (W)
This input signal is used to control whether the
memory is write protected. When W is held Low,
writes to the memory are disabled, but other oper-
ations remain enabled. No action on this signal, or
on the Write Enable Latch (WEL) bit, can interrupt
a Write cycle that has already started.
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M95040, M95020, M95010
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
CS3
CS2
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
SPI Memory
Device
SPI Memory
Device
C Q D
C Q D
AI03746D
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
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M95040, M95020, M95010
Figure 5. SPI Modes Supported
CPOL
CPHA
C
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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