SGRAM MODULE
M965G0225MP(Q)0 / M966G0225MP(Q)0
M965G0225MP(Q)0 / M966G0225MP(Q)0 SGRAM SODIMM
2Mx64 SGRAM SODIMM based on 1Mx32, 2K Refresh, 3.3V Synchronous Graphic RAMs
GENERAL DESCRIPTION
The Samsung M965(6)G0225MP(Q)0 is a 2M bit x 64 Syn-
chronous Graphic RAM high density memory module. The
Samsung M965(6)G0225MP(Q)0 consists of four CMOS 1M x
32 bit Synchronous Graphic RAMs in 100pin QFP packages
mounted on a 144pin glass-epoxy substrate. Five 0.1uF
decoupling capacitors are mounted on the printed circuit board
for each Synchronous GRAM. The M965(6)G0225MP(Q)0 is a
Small Outline Dual In-line Memory Module and is intended for
mounting into 144-pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
•
•
•
•
•
•
•
FEATURE
• Performance range
Part NO.
M965(6)G0225MP(Q)0-C50
M965(6)G0225MP(Q)0-C60
M965(6)G0225MP(Q)0-C70
M965(6)G0225MP(Q)0-C80
Max. Freq. (t
CC
)
200MHz (5ns) @CL=3
166MHz (6ns) @CL=3
143MHz (7ns) @CL=3
125MHz (8ns) @CL=3
* M965(6)G0225MP0 : based on PQFP Component
M965(6)G0225MQ0 : based on TQFP Component
Burst Mode Operation
BLOCK-WRITE and Write-per-bit capability
Independent byte operation via DQM0 ~ 7
Auto & Self Refresh Capability (2048 cycles / 32ms)
LVTTL compatible inputs and outputs
Single 3.3V±0.3V power supply
MRS cycle with address key programs.
CAS Latency (2, 3)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• Optional Serial PD with EEPROM (M966G0225)
• Resistor Strapping Options for speed and CAS Latency
• PCB : Height(1250mil), double sided components
PIN CONFIGURATIONS (Front Side / Back Side)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
V
SS
DQ63
DQ61
DQ59
DQ57
V
DD
DQ55
DQ53
DQ51
DQ49
V
SS
DQM7
DQM5
V
DD
DQ47
DQ45
DQ43
DQ41
V
SS
DQ39
DQ37
DQ35
DQ33
V
DD
RSVD
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
V
SS
DQ62
DQ60
DQ58
DQ56
V
DD
DQ54
DQ52
DQ50
DQ48
V
SS
DQM6
DQM4
V
DD
DQ46
DQ44
DQ42
DQ40
V
SS
DQ38
DQ36
DQ34
DQ32
V
DD
RSVD
Pin
Front
Pin
Back
Pin
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Front
DQ31
DQ29
DQ27
DQ25
V
SS
DQ23
DQ21
DQ19
DQ17
V
DD
DQM3
DQM1
V
SS
DQ15
DQ13
DQ11
DQ9
V
DD
DQ7
DQ5
DQ3
DQ1
V
SS
**SDA
V
DD
Pin
Back
PIN NAMES
Pin Name
A0 ~ A10
BA
DQ0 ~ 63
CLK0, CLK1
CKE
CS0, CS1
RAS
CAS
WE
DSF
DQM0 ~ 7
V
DD
V
SS
**SDA
**SBA
**SCL
RSVD
RFU
NC
Function
Address Input(multiplexed)
Bank Select Address
Data Input / Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Define Special Function
DQM
Power Supply (3.3V)
Ground
Serial Address Data I/O
EEPROM Device Address
Serial Clock
Reserved
Reserved for future use
No Connection
96 DQ30
98 DQ28
100 DQ26
102 DQ24
104
V
SS
106 DQ22
108 DQ20
110 DQ18
112 DQ16
114
V
DD
116 DQM2
118 DQM0
120
V
SS
122 DQ14
124 DQ12
126 DQ10
128 DQ8
130
V
DD
132 DQ6
134 DQ4
136 DQ2
138 DQ0
140
V
SS
142 **SCL
144
V
DD
Voltage Key
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
RSVD
RSVD
V
SS
DSF
RFU
RFU
V
DD
CS1
RAS
WE
V
SS
CLK1
V
DD
RSVD
A10
BA
A7
V
SS
A5
A3
A1
V
DD
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
RSVD
RSVD
V
SS
RFU
RFU
**SBA
V
DD
CS0
CAS
CKE
V
SS
CLK0
V
DD
RSVD
A9
A8/AP
A6
V
SS
A4
A2
A0
V
DD
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.
SGRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System Clock
Chip Select
M965G0225MP(Q)0 / M966G0225MP(Q)0
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power and ground for the input buffers and the core logic.
CKE
Clock Enable
A0 ~ A10
BA
RAS
CAS
WE
DQM0 ~ 7
DQ0 ~ 63
DSF
V
DD
/V
SS
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply/Ground
RESISTOR STRAPPING OPTIONS
Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information
for each clock frequency is indicated in the section titled
AC CHARATERISTICS.
Clock Frequency and Memory Timing
Cycle Time
8 ns
7 ns
6 ns
5 ns
DQ30
1
1
0
0
DQ29
0
1
0
1
CAS Latency
CAS Latency
3
2 and 3
DQ31
0
1
SGRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
•
•
M965G0225MP(Q)0 / M966G0225MP(Q)0
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
U0
•
•
•
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
U2
DQM4
DQ32
•
•
•
DQ39
DQM5
DQ40
•
•
•
DQ47
DQM6
DQ48
•
•
•
DQ55
DQM7
DQ56
•
•
•
DQ63
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
U1
•
•
•
DQM0
DQ0
•
•
•
DQ7
DQM1
DQ8
•
•
•
DQ15
DQM2
DQ16
•
•
•
DQ23
DQM3
DQ24
•
•
•
DQ31
U3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
10Ω
CKE
RAS
CAS
WE
DSF
A(10:0)
BA
U0 to U3
U0 to U3
U0 to U3
U0 to U3
U0 to U3
U0 to U3
U0 to U3
CLK0
CLK1
0Ω
U0, U1
U2, U3
Serial PD
SCL
A0
A1
A2
•
SDA
V
DD
Vss
•
•
•
•
•
•
Five 0.1uF Capacitors
per SGRAM device
To all SGRAMs
SBA
.
.
.
V
SS
* Serial PD is optional
SGRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
M965G0225MP(Q)0 / M966G0225MP(Q)0
(Voltages referenced to V
SS
)
Symbol
V
IN
, V
OUT
V
DD
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
4
50
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Output loading conditon
Symbol
V
DD
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
Min
3.0
2.0
-0.3
2.4
-
-40
-20
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
40
20
See Figure 1
Unit
V
V
V
V
V
uA
uA
Note 1
I
OH
= -2mA
I
OL
= 2mA
Note 2
Note 3
Note
Note 4
Note :
1. V
IL
(min.) = -1.5V AC (pulse width
≤
5ns)
2. Any input 0V
≤
V
IN
≤
V
DD
+ 0.3V, all other pins are not under test = 0V.
3. Dout is disabled, 0V
≤
V
OUT
≤
V
DD
4. The VDD condition of M965(6)G0225MP(Q)0-C50/60 is 3.135V~3.6V.
CAPACITANCE
(V
CC
= 3.3V, T
A
= 25°C, f = 1MHz)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT
Min
-
-
-
-
-
-
Max
26
26
18
18
18
20
Unit
pF
pF
pF
pF
pF
pF
Parameter
Input capacitance (A0 ~ A10, BA)
Input capacitance (RAS, CAS, WE, CKE, DSF)
Input capacitance (CLK0,CLK1)
Input capacitance (CS0,CS1)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
SGRAM MODULE
DC CHARACTERISTICS
M965G0225MP(Q)0 / M966G0225MP(Q)0
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70°C, V
IH(min)
/V
IL(max)
=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
CAS
Latency
3
2
Speed
-50
-60
-70
-80
mA
-
-
8
8
120
mA
60
12
12
200
mA
120
3
2
3
2
Self Refresh Current
Operating Current
(One Bank Block Write)
I
CC6
I
CC7
CKE
≤
0.2V
t
CC
≥
t
CC
(min), I
o
=0mA, t
BWC
(min)
640 580 520 460
-
-
-
380
mA
mA
mA
3
-
360
mA
2
Unit Note
I
CC1
Burst Length =1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
o
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
&
CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
& ≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
o
= 0 mA, Page Burst
All bank Activated, t
CCD
= t
CCD
(min)
t
RC
≥
t
RC
(min)
460 420 380 360
Precharge Standby Current in I
CC2
P
power-down mode
I
CC2
PS
I
CC2
N
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
I
CC3
P
I
CC3
PS
I
CC3
N
I
CC3
NS
mA
I
CC4
mA
2
I
CC5
800 720 640 600
-
-
8
520 460 400 360
-
600
Note :
1. Unless otherwise notes, Input level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
) in LVTTL.
2. Measured with outputs open. Address are changed only one time during tcc(min).
3. Refresh period is 32ms. Address are changed only one time during tcc(min).
嵌入式系统
