Freescale Semiconductor
Product Brief
MAC7105PB
Rev. 2, 09/2004
MAC71x5 Microcontroller Device
Product Brief
Covers MAC7105, MAC7115, MAC7125, MAC7135
32-bit Embedded Controller Division
MAC71x5 microcontrollers (MCUs) are members of a
pin-compatible family of 32-bit Flash-memory-based
devices developed specifically for embedded automotive
applications. The pin-compatible family concept enables
users to select between different memory and peripheral
options for scalable designs. All MAC71x5 devices are
composed of an ARM7TDMI-S™ 32-bit central
processing unit, 768 Kbyte of high performance
embedded Flash memory for program storage, an
optional 32 Kbytes of embedded Flash for data and/or
program storage, and 40 Kbytes of RAM.
As shown in
Table 1
and
Figure 1,
the MAC71x5 family
is implemented with a variety of on-chip peripherals. An
enhanced DMA (eDMA) controller executes in parallel
with the CPU to improve the performance of data
transfers between memory and many of the peripherals.
DMA transfers may be triggered by various peripheral
events, such as data frame transmission or reception,
elapsed timer periods, and analog-to-data conversion
completions. The peripheral set includes enhanced
asynchronous serial communications interfaces (eSCI)
with Local Interconnect Network (LIN) support
hardware to reduce interrupt overhead, serial peripheral
interfaces (DSPI) with flexible chip selects and fast baud
Table of Contents
Block Diagram.........................................................3
Features ..................................................................3
Modes of Operation ................................................8
Chip Configuration Modes...................................8
Low-Power Modes ...............................................9
Functional Overview ...............................................9
32-bit ARM7TDMI-S RISC Core..........................9
Enhanced Direct Memory Access (eDMA) and
Channel Multiplexer (DMA MUX) ........................9
4.3
External Interface Module (EIM)........................10
4.4
Common Flash Module (CFM) ..........................10
4.5
Interrupt Controller (INTC).................................10
4.6
Port Integration Module (PIM) ...........................10
4.7
Analog-to-Digital Converters (ATD) ...................11
4.8
CAN 2.0 Software Compatible (FlexCAN)
Modules.............................................................11
4.9
Enhanced Modular I/O Subsystem (eMIOS) .....12
4.10 Serial Peripheral Interfaces (DSPI) ...................12
4.11 Enhanced Serial Communications Interfaces
(eSCI) ................................................................12
4.12 Inter-Integrated Circuit (I
2
C) Bus Module ..........13
4.13 Periodic Interrupt Timer (PIT) Module ...............13
4.14 Miscellaneous Control Module (MCM) and
Cross-Bar Switch (XBS) ....................................13
4.15 System Services Module (SSM)........................13
4.16 Voltage Regulator Module (VREG)....................14
4.17 System Clocks (OSC and CRG)......14
4.18 Development Support......................14
5 Documentation and Ordering..............15
1
2
3
3.1
3.2
4
4.1
4.2
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
• Preliminary
Table 1. MAC71x5 Device Derivatives
MAC7105
Program Flash
Data Flash
SRAM
External Bus
ATD Modules
(1)
CAN Modules
MAC7115
MAC7125
MAC7135
768 Kbyte
32 Kbytes
40 Kbytes
A
B
A
B
C
D
A
B
C
D
A
B
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(2)
Yes
(2)
Yes
Yes
—
Yes
Yes
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(2)
Yes
(2)
Yes
(2)
Yes
(4)
Yes
Yes
16 channels, 16-bit
10 channels, 24-bit
112
85
144 LQFP
112 LQFP
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
(3)
Yes
(3)
Yes
eSCI Modules
DSPI Modules
I
2
C Module
eMIOS Module
Timer Module
GPIO Pins (max.)
Package
112
144 LQFP
144
208 MAP BGA
NOTES:
1. 16 channels, 8/10-bit, per module.
2. Four chip select signals available.
3. Eight chip select signals available.
4. Three chip select signals available.
rate switching, inter-integrated circuit (I
2
C™) bus controllers, FlexCAN interfaces with flexible message
buffering, an enhanced modular I/O subsystem (eMIOS) with sixteen high-performance 16-bit timers, one
or two sixteen-channel 10-bit analog-to-digital converters (ATD), general-purpose timers (Programmable
Interrupt Timer (PIT)) and two special-purpose timers (Real Time Interrupt (RTI) and Software Watchdog
Timer (SWT)). The peripherals share a large number of general purpose input-output (GPIO) pins, all of
which are bidirectional and available with interrupt capability to trigger wake-up from low-power chip
modes.
Internal data paths between the CPU core, eDMA, memory and peripherals are all 32 bits wide, further
improving performance for 32-bit applications. The MAC7115 and MAC7135 also offer a 16-bit wide
external data bus with 22 address lines, allowing access of up to 4 MBytes of external address space. The
inclusion of a programmable PLL module allows power consumption and performance to be adjusted to suit
operational requirements. Both E-ICE and Nexus 2 interfaces are implemented to support development and
debug tool chains.
MAC71x5 devices include an on-chip multi-output voltage regulator, thus requiring only a single external
3.3V to 5V power supply. The maximum operating range of devices in the family covers a junction
temperature of –40° C to 150° C and CPU clock frequencies up to 50 MHz (below 105° C, frequency is
limited to 40 MHz @ 150° C). Packaging options range from 112-pin LQFP up to 208-pin MAP BGA.
MAC71x5 Microcontroller Device Product Brief, Rev. 2
2
Preliminary
Freescale Semiconductor
Block Diagram
1
Block Diagram
Standard Product Platform (SPP)
E-ICE
JTAG
NEXUS II
eDMA
MCM
ARM7 TDMI-S
FLASH Controller
XBS
768 KB Program FLASH
32 KB Data FLASH
AIPS
SRAM Controller
40 KB SRAM
EIM
INTC
I
2
C
VREG
OSC & CRG
PIM
DMA MUX
PIT
SSM
FlexCAN A
eMIOS
ATD A
ATD B
Note:
Refer to
Table 1
for details of peripheral and memory configurations
FlexCAN B
FlexCAN C
FlexCAN D
DSPI A
DSPI B
eSCI A
eSCI B
eSCI C
eSCI D
Intelligent Peripheral
Subsystem (IPS)
Figure 1. MAC71x5 Device Block Diagram
2
Features
As shown in
Figure 1,
MAC7100 family devices are organized into two major blocks:
• Standard Product Platform (SPP) — The SPP consists of the ARM7TDMI-S processor core and
an enhanced direct memory access controller connected to a high-performance 32-bit bus through
a cross-bar bus switch to the rest of the chip modules. The SPP also contains an interrupt
controller, SRAM controller, Flash memory controller, external bus interface, peripheral bus
bridge, and miscellaneous control module.
• Intelligent Peripheral Subsystem (IPS) — The IPS consists of the voltage regulator, oscillator,
clock and reset generator, port integration module, DMA request multiplexer, analog to digital
converter(s), enhanced modular I/O subsystem, enhanced serial communications controllers,
serial peripheral interface(s), FlexCAN controller(s), an inter-integrated circuit (I
2
C) bus
controller, programmable interrupt timer, and system services module.
MAC71x5 Microcontroller Device Product Brief, Rev. 2
Freescale Semiconductor
Preliminary
3
Features
The primary features of MAC71x5 integrated processors include the following:
• General MAC7100 family features
— Up to 50 MHz operating frequency
— RISC core, eDMA, and memory connected via high performance 32-bit bus
— Separate 32-bit bus interface for slower system peripherals
— External bus interface available to support off-chip devices (on selected devicesMAC7115
and MAC7135 only)
• 32-bit ARM7TDMI-S RISC core
— Supports 32-bit and 16-bit (THUMB) instruction sets for code size efficiency
— 32 bit wide data path
— Alternate general-purpose registers
— Byte (8-bit), halfword (16-bit), and word (32-bit) data types supported
• Enhanced Direct Memory Access (eDMA) and Channel Multiplexer (DMA MUX)
— Supports transfers between system memories, external devices, peripheral modules (ATD,
DSPI, eMIOS, eSCI, and I
2
C), and general-purpose I/O using a dual-address transfer protocol
— DMA MUX allows assignment of any DMA request source to any available eDMA channel
— Programmable transfer control descriptors stored in local eDMA memory
— Programmable source and destination address with configurable offset
— Programmable transfer size and nesting via 32-bit major and 16-bit minor loop counters
— Different final source and destination addresses allow circular queue operation
— Programmable priority levels for each channel
— Bandwidth control for each channel
— Independently programmable read/write sizes
— Periodic triggering of up to 8 channels
• Memory options
— 768 Kbyte program Flash EEPROM
– 50 MHz single-cycle non-sequential access for aligned halfword and aligned word data
– State machine controlled program/erase operations
– Internal programming voltage generator
– Small Flash sector protection sizes
– Configurable flexible Flash protection fields
– Protection violation flag
– 10,000 program / erase cycle endurance
– 15-year data retention
— 32 Kbyte data Flash EEPROM
– 16-bit wide memory accessed via peripheral bus interface
– Relocatable to page zero to provide data Flash boot operation
– State machine controlled program/erase operations
– Internal programming voltage generator
– Up to 8 protected sectors in the data Flash
– 10,000 program / erase cycle endurance
– 15-year data retention
— 40 Kbyte RAM
– Single cycle accesses to RAM for byte, halfword, and word reads and writes
MAC71x5 Microcontroller Device Product Brief, Rev. 2
4
Preliminary
Freescale Semiconductor
Features
•
•
•
•
•
Interrupt Controller (INTC)
— 64 vectored interrupt sources
— 44 peripheral, 17 DMA, 1 software watchdog timer, 2 external sources
— 16 programmable interrupt priorities for every source, even in low-power modes
— Multiple level interrupt nesting, with hardware support for first nesting level
— Normal and Fast interrupt support
General purpose input/output
— Up to 144 port pins shared with peripherals
— All ports are 16 bits wide, with pins bidirectional and independently selectable
— Wake-up interrupt available on all port pins
Analog-to-Digital Converter(s) (ATD)
— One or two ATD modules
— 16 analog input channels per ATD module
— 10-bit resolution with
±
2 counts accuracy
— 7µS minimum conversion time
— Internal sample and hold circuitry
— Programmable input sample time for various source impedances
— Queued conversion sequences supported by eDMA controller
— Unused analog channels can be used as digital I/O
— External and on-chip sample triggers, including periodic triggering via the PIT module
— Synchronized sampling between ATD modules using external or on-chip triggers
CAN 2.0 software compatible modules (FlexCAN)
— Four CAN modules
— Full implementation of the CAN 2.0 protocol specification
— Programmable bit rate up to 1M bps
— Up to 32 flexible message buffers of 0 to 8 bytes data length for each module
— All message buffers configurable for either Rx/Tx
— Unused message buffer space can be used as general purpose RAM
— Supports standard or extended messages
— Time stamp, based on a 16-bit free-running counter
— Maskable interrupts, including low-power mode wake up on bus activity
— Programmable I/O modes
Enhanced Modular I/O Subsystem (eMIOS)
— 16 unified channels, each of which can be enabled for eDMA service
— Three 16-bit counter buses, with synchronization between timebases
— One global prescaler plus prescaler available on each channel
— Channels can be individually disabled to assist with power saving
— Fourteen channel operating modes available:
– General-purpose input/output
– Single-action input capture
– Single-action output compare
– Input pulse width measurement
– Input period measurement
– Double-action output compare
MAC71x5 Microcontroller Device Product Brief, Rev. 2
Freescale Semiconductor
Preliminary
5
