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MAX1434ECQ

ADC, Proprietary Method, 10-Bit, 8 Func, 1 Channel, Serial Access, PQFP100, 14 X 14 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-100

器件类别:模拟混合信号IC    转换器   

厂商名称:Maxim(美信半导体)

厂商官网:https://www.maximintegrated.com/en.html

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
Maxim(美信半导体)
零件包装代码
QFP
包装说明
14 X 14 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-100
针数
100
Reach Compliance Code
not_compliant
ECCN代码
EAR99
转换器类型
ADC, PROPRIETARY METHOD
JESD-30 代码
S-PQFP-G100
JESD-609代码
e0
长度
14 mm
最大线性误差 (EL)
0.0977%
湿度敏感等级
3
模拟输入通道数量
1
位数
10
功能数量
8
端子数量
100
最高工作温度
85 °C
最低工作温度
-40 °C
输出位码
BINARY, 2\'S COMPLEMENT BINARY
输出格式
SERIAL
封装主体材料
PLASTIC/EPOXY
封装代码
HVFQFP
封装形状
SQUARE
封装形式
FLATPACK, HEAT SINK/SLUG, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度)
245
认证状态
Not Qualified
采样速率
50 MHz
采样并保持/跟踪并保持
TRACK
座面最大高度
1.6 mm
标称供电电压
1.8 V
表面贴装
YES
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn85Pb15)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
14 mm
文档预览
19-3647; Rev 0; 4/05
KIT
ATION
EVALU
BLE
AVAILA
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
Features
Excellent Dynamic Performance
61dB SNR at 5.3MHz
84dBc SFDR at 5.3MHz
94dB Channel Isolation
Ultra-Low Power
96mW per Channel (Normal Operation)
Serial LVDS Outputs
Pin-Selectable LVDS/SLVS (Scalable Low-Voltage
Signal) Mode
LVDS Outputs Support Up to 30 Inches FR-4
Backplane Connections
Test Mode for Digital Signal Integrity
Fully Differential Analog Inputs
Wide Differential Input Voltage Range (1.4V
P-P
)
On-Chip 1.24V Precision Bandgap Reference
Clock Duty-Cycle Equalizer
Compact, 100-Pin TQFP Package with Exposed
Paddle
Evaluation Kit Available (Order MAX1434EVKIT)
General Description
The MAX1434 octal, 10-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction incorporating a
fully differential signal path. This ADC is optimized for
low-power and high-dynamic performance in medical
imaging instrumentation and digital communications
applications. The MAX1434 operates from a 1.8V single
supply and consumes only 767mW (96mW per chan-
nel) while delivering a 61dB (typ) signal-to-noise ratio
(SNR) at a 5.3MHz input frequency. In addition to low
operating power, the MAX1434 features a power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
full-scale range of the ADC. A flexible reference struc-
ture allows the use of an external reference for applica-
tions requiring increased accuracy or a different input
voltage range. The reference architecture is optimized
for low noise.
A single-ended clock controls the data-conversion
process. An internal duty-cycle equalizer compensates
for wide variations in clock duty cycle. An on-chip PLL
generates the high-speed serial low-voltage differential
signal (LVDS) clock.
The MAX1434 has self-aligned serial LVDS outputs for
data, clock, and frame-alignment signals. The output
data is presented in two’s complement or binary format.
The MAX1434 offers a maximum sample rate of
50Msps. See the
Pin-Compatible Versions
table below
for 12-bit versions. This device is available in a small,
14mm x 14mm x 1mm, 100-pin TQFP package with
exposed paddle and is specified for the extended
industrial (-40°C to +85°C) temperature range.
MAX1434
Ordering Information
PART
MAX1434ECQ
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
100 TQFP-EP*
(14mm x 14mm x 1mm)
*EP
= Exposed paddle.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
PART
MAX1436
MAX1437
MAX1438**
Pin-Compatible Versions
SAMPLING RATE
(Msps)
40
50
65
RESOLUTION
(BITS)
12
12
12
**Future
product—contact factory for availability.
Pin Configuration appears at the end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
MAX1434
ABSOLUTE MAXIMUM RATINGS
AV
DD
to GND.........................................................-0.3V to +2.0V
CV
DD
to GND ........................................................-0.3V to +3.6V
OV
DD
to GND ........................................................-0.3V to +2.0V
IN_P, IN_N to GND...................................-0.3V to (AV
DD
+ 0.3V)
CLK to GND .............................................-0.3V to (CV
DD
+ 0.3V)
OUT_P, OUT_N, FRAME_,
CLKOUT_ to GND................................-0.3V to (OV
DD
+ 0.3V)
DT, SLVS/LVDS, LVDSTEST, PLL_,
T/B,
REFIO, REFADJ, CMOUT to GND .......-0.3V to (AV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
100-Pin TQFP 14mm x 14mm x 1mm
(derated 47.6mW/°C above +70°C)........................3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 3.3V, GND = 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF, C
REFP
to GND = 10µF,
C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY (Note 2)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range
Common-Mode Voltage Range
Common-Mode Voltage Range
Tolerance
Differential Input Impedance
Differential Input Capacitance
CONVERSION RATE
Maximum Conversion Rate
Minimum Conversion Rate
Data Latency
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT) (Note 2)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
(First 4 Harmonics)
Effective Number of Bits
Spurious-Free Dynamic Range
SNR
SINAD
ENOB
SFDR
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
77
60
60
61.1
61.1
61.1
61.1
9.9
9.9
84
85
dB
dB
dB
dBc
f
SMAX
f
SMIN
50
4.8
6.5
MHz
MHz
Cycles
R
IN
C
IN
V
ID
V
CMO
(Note 3)
Switched capacitor load
Differential input
1.4
0.76
±50
2
12.5
V
P-P
V
mV
kΩ
pF
-3
N
INL
DNL
No missing codes over temperature
10
±0.1
±0.1
±1
±0.5
±0.7
+2
Bits
LSB
LSB
%FS
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 3.3V, GND = 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF, C
REFP
to GND = 10µF,
C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
Total Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Aperture Jitter
Aperture Delay
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
Over-Range Recovery Time
INTERNAL REFERENCE
REFADJ Internal Reference-Mode
Enable Voltage
REFADJ Low-Leakage Current
REFIO Output Voltage
Reference Temperature
Coefficient
EXTERNAL REFERENCE
REFADJ External Reference-
Mode Enable Voltage
REFADJ High-Leakage Current
REFIO Input Voltage
REFIO Input Voltage Tolerance
REFIO Input Current
CMOUT Output Voltage
CLOCK INPUT (CLK)
Input High Voltage
Input Low Voltage
Clock Duty Cycle
Clock Duty-Cycle Tolerance
Input Leakage
Input Capacitance
DI
IN
DC
IN
Input at GND
Input at AV
DD
5
V
CLKH
V
CLKL
50
±30
5
80
0.8 x
CV
DD
0.2 x
CV
DD
V
V
%
%
µA
pF
I
REFIO
V
CMOUT
COMMON-MODE OUTPUT (CMOUT)
0.76
V
(Note 4)
AV
DD
-
0.1V
200
1.24
±5
<1
V
µA
V
%
µA
V
REFIO
TC
REFIO
1.18
(Note 4)
1.5
1.24
120
1.30
0.1
V
mA
V
ppm/°C
t
OR
SYMBOL
THD
IMD
IM3
t
AJ
t
AD
SSBW
LSBW
CONDITIONS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
1
= 5.3MHz at -6.5dBFS
f
2
= 6.3MHz at -6.5dBFS
f
1
= 5.3MHz at -6.5dBFS
f
2
= 6.3MHz at -6.5dBFS
Figure 11
Figure 11
Input at -20dBFS
Input at -0.5dBFS
IN_P = IN_N
R
S
= 25Ω, C
S
= 50pF
MIN
TYP
-89
-91
86.0
92.9
<0.4
1
100
100
0.058
1
-77
MAX
UNITS
dBc
dBc
dBc
ps
RMS
ns
MHz
MHz
LSB
RMS
Clock
cycle
MAX1434
_______________________________________________________________________________________
3
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
MAX1434
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 3.3V, GND = 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF, C
REFP
to GND = 10µF,
C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.8 x
AV
DD
0.2 x
AV
DD
Input at GND
Input at AV
DD
5
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω
R
TERM
= 100Ω
R
TERM
= 100Ω, C
LOAD
= 5pF
R
TERM
= 100Ω, C
LOAD
= 5pF
(Note 5)
250
1.125
350
350
205
220
320
320
100
20
1.7
1.7
1.7
PD = 0
AV
DD
Supply Current
I
AVDD
f
IN
= 19.3MHz PD = 0, DT = 1
at -0.5dBFS
PD = 1, power-down,
no clock input
PD = 0
OV
DD
Supply Current
I
OVDD
f
IN
= 19.3MHz PD = 0, DT = 1
at -0.5dBFS
PD = 1, power-down,
no clock input
CV
DD
is used only to bias ESD-protection
diodes on CLK input, Figure 2
f
IN
= 19.3MHz at -0.5dBFS
1.8
1.8
1.8
348
348
1.54
78
100
566
0
767
882
100
1.9
1.9
3.6
390
450
1.375
5
80
TYP
MAX
UNITS
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS, PD,
T/B)
Input High Threshold
Input Low Threshold
Input Leakage
Input Capacitance
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
POWER-DOWN
PD Fall to Output Enable
PD Rise to Output Disable
POWER REQUIREMENTS
AV
DD
Supply Voltage Range
OV
DD
Supply Voltage Range
CV
DD
Supply Voltage Range
AV
DD
OV
DD
CV
DD
V
V
V
mA
mA
mA
µA
mA
mW
t
ENABLE
t
DISABLE
ms
ns
V
IH
V
IL
DI
IN
DC
IN
V
OHDIFF
V
OCM
t
RL
t
FL
V
OHDIFF
V
OCM
t
RS
t
FS
V
V
µA
pF
mV
V
ps
ps
mV
V
ps
ps
LVDS OUTPUTS (OUT_P, OUT_N), SLVS/LVDS = 0
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
CV
DD
Supply Current
Power Dissipation
I
CVDD
P
DISS
4
_______________________________________________________________________________________
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 3.3V, GND = 0, external V
REFIO
= 1.24V, C
REFIO
to GND = 0.1µF, C
REFP
to GND = 10µF,
C
REFN
to GND = 10µF, f
CLK
= 50MHz (50% duty cycle), V
DT
= 0, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
(t
SAMPLE
/
20)
- 0.15
t
SAMPLE
/
10
t
SAMPLE
/
10
(t
SAMPLE
/
20)
- 0.15
(3t
SAMPLE
/
5)
+ 1.1
-94
±0.1
±0.25
(t
SAMPLE
/
20)
+ 0.15
(3t
SAMPLE
/
5)
+ 2.6
TYP
MAX
(t
SAMPLE
/
20)
+ 0.15
UNITS
MAX1434
TIMING CHARACTERISTICS (Note 6)
Data Valid to CLKOUT Rise/Fall
t
OD
Figure 5 (Note 7)
ns
CLKOUT Output-Width High
CLKOUT Output-Width Low
t
CH
t
CL
Figure 5
Figure 5
ns
ns
FRAME Rise to CLKOUT Rise
t
CF
Figure 4 (Note 7)
ns
Sample CLK Rise to FRAME Rise
Crosstalk
Gain Matching
Phase Matching
t
SF
Figure 4 (Note 7)
(Note 2)
ns
dB
dB
Degrees
C
GM
C
PM
f
IN
= 5.3MHz (Note 2)
f
IN
= 5.3MHz (Note 2)
Note 1:
Specifications at T
A
+25°C are guaranteed by production testing. Specifications at T
A
< +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 2:
See definition in the
Parameter Definition
section at the end of this data sheet.
Note 3:
See the
Common-Mode Output (CMOUT)
section.
Note 4:
Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AV
DD
directly to disable the internal
bandgap reference and enable external reference mode.
Note 5:
Measured using C
REFP
to GND = 1µF and C
REFN
to GND = 1µF. t
ENABLE
time may be lowered by using smaller capacitor values.
Note 6:
Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7:
Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(AV
DD
= 1.8V, OV
DD
= 1.8V, CV
DD
= 3.3V, GND = 0, internal reference, differential input at -0.5dBFS, f
IN
= 5.3MHz, f
CLK
= 50MHz
(50% duty cycle), V
DT
= 0, C
LOAD
= 10pF, T
A
= +25°C, unless otherwise noted.)
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1434 toc01
FFT PLOT
(16,384-POINT DATA RECORD)
MAX1434 toc02
CROSSTALK
(16,384-POINT DATA RECORD)
-10
-20
AMPLITUDE (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
f
IN(IN2)
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
f
IN(IN1)
= 5.304814MHz
f
IN(IN2)
= 24.0997119MHz
CROSSTALK = 94dB
MAX1434 toc03
0
-10
-20
AMPLITUDE (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
0
5
10
15
20
HD2
HD3
f
CLK
= 50.1523789MHz
f
IN
= 5.304814MHz
A
IN
= -0.5dBFS
SNR = 61.146dB
SINAD = 61.139dB
THD = -89.316dBc
SFDR = 84.455dBc
0
-10
-20
AMPLITUDE (dBFS)
-30
-40
-50
-60
-70
-80
-90
-100
HD2
HD3
f
CLK
= 50.152379MHz
f
IN
= 24.0997119MHz
A
IN
= -0.5dBFS
SNR = 61.118dB
SINAD = 61.112dB
THD = -91.363dBc
SFDR = 85.069dBc
0
25
0
5
10
15
20
25
0
5
10
15
20
25
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
5
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