19-2062; Rev 0; 5/01
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
General Description
The MAX3877/MAX3878 are compact, low-power clock
recovery and data retiming ICs for 2.488Gbps SONET/
SDH applications. The fully integrated phase-locked
loop (PLL) recovers a synchronous clock signal from
the serial NRZ data input, which is retimed by the
recovered clock. An additional 2.488Gbps serial input
is available for system loopback diagnostic testing, or
this input can be connected to a 155MHz reference
clock to maintain a valid clock output in the absence of
data transitions. The MAX3877/MAX3878 provide verti-
cal threshold and phase-adjust control to optimize sys-
tem BER in DWDM applications.
These devices provide both loss-of-lock (LOL) and
loss-of-signal (LOS) monitors. Differential CML outputs
are provided for both clock and data signals on the
MAX3877, and differential PECL outputs are provided
for clock and data signals on the MAX3878.
The MAX3877/MAX3878 are designed for both section-
regenerator and terminal-receiver applications in OC-
48/STM-16 transmission systems. Their jitter performance
exceeds all of the SONET/SDH specifications. These
devices operate from a single +3.0V to +3.6V supply over
a -40°C to +85°C temperature range. Typical power con-
sumption is only 540mW with a +3.3V supply (MAX3878).
They are available in a 32-pin TQFP-EP package with an
exposed pad, as well as in die form.
Features
o
Exceeds ANSI, ITU, and Bellcore SONET/SDH
Specifications
o
Adjustable Input Threshold (±180mV)
o
10mVp-p to 1.2Vp-p Differential Input Range
o
540mW Power Dissipation (at +3.3V)
o
Fully Integrated Clock Recovery and Data
Retiming
o
Optional Holdover Capability (Using External
Reference Clock)
o
0.003UI
RMS
Clock Jitter Generation
o
Tolerates >2000 Consecutive Identical Digits
o
Additional 2.488Gbps Input for Diagnostic
Loopback Testing
o
Differential PECL or CML Data and Clock Outputs
o
Loss-of-Signal Indicator
o
Loss-of-Lock Indicator
MAX3877/MAX3878
Ordering Information
PART
MAX3877EHJ
MAX3877E/D***
MAX3878EHJ
MAX3878E/D***
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP-EP*
DICE**
32 TQFP-EP*
DICE**
Applications
Long Haul and Metro Systems with
Optical Amplification
DWDM Transmission Systems
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
* Exposed pad
** Dice are designed to operate over this range, but are tested
and guaranteed at T
A
= +25°C only. contact factory for avail-
ability.
*** Future product—contact factory for availability.
Pin Configuration
CPWD+
CPWD-
TOP VIEW
PHADJ
GND
FIL+
LOS
26
32
GND
THADJ
V
CC
SDI-
SDI+
V
CC
SIS
LREF
1
2
3
4
5
6
7
8
9
GND
31
30
29
28
27
LOL
25
24
V
CC
23
SDO+
22
SDO-
21
V
CC
20
V
CC
19
SCLKO+
18
SCLKO-
17
V
CC
16
GND
MAX3877
MAX3878
FIL-
10
GND
11
V
CC
12
SLBI-
13
SLBI+
14
V
CC
15
V
CC
Typical Operating Circuit appears at end of data sheet.
TQFP
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
MAX3877/MAX3878
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +5.5V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-) ..........(V
CC
- 0.8V) to (V
CC
+ 0.5V)
Input Current Levels
(SDI+, SDI-, SLBI+, SLBI-)............................-16mA to +10mA
PECL Output Current Levels
(SDO+, SDO-, SCLKO+, SCLKO-) .....................0mA to 56mA
CML Output Current Level
(SDO+, SDO-, SCLKO+, SCLKO-) ...............................±22mA
Current into LOS,
LOL
.....................................-600µA to +4mA
Voltage at LOS, SIS, PHADJ, THADJ, CPWD+, CPWD-,
LOL,
FIL+, FIL-, LREF.............................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
32-Pin TQFP-EP (derate 22.2mW/°C above +85°C) ..1444mW
Operating Temperature Range
MAX3877/MAX3878EHJ ..................................-40°C to +85°C
Operating Junction Temperature Range (die) ..-55°C to +150°C
Storage Temperature Range .............................-65°C to +150°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.) (Note 1)
PARAMETER
SUPPLY CURRENT
MAX3877 (Note 2)
Supply Current
INPUT SPECIFICATION
(SDI±, SLBI±)
Differential Input Voltage (SDI±)
Differential System Loopback
Input Voltage Range (SLBI±)
Single-Ended Input Voltage
(SDI±, SLBI±)
Input Termination to V
CC
(SDI±, SLBI±)
V
ID
V
ID
V
IS
R
IN
Figure 1 (Note 3)
10
50
V
CC
-
0.6
52
1200
1200
V
CC
+
0.3
mVp-p
mVp-p
V
Ω
I
CC
MAX3878 (Note 2)
163
250
175
262
mA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3878 PECL OUTPUT SPECIFICATION
(SDO±, SCLKO±)
PECL Output High Voltage
(SDO±, SCLKO±)
T
A
= 0°C to +85°C
T
A
= -40°C
T
A
= 0°C to +85°C
T
A
= -40°C
V
CC
-
1.025
V
CC
-
1.085
V
CC
-
1.81
V
CC
-
1.83
V
CC
-
0.88
V
CC
-
0.88
V
CC
-
1.62
V
CC
-
1.556
V
PECL Output Low
Voltage (SDO±, SCLKO±)
V
MAX3877 CML OUTPUT SPECIFICATION
(SDO±, SCLKO±)
CML Differential Output Swing
CML Differential Output
Impedance
CML Output Common-Mode
Voltage
R
O
DC-coupling (R
L
= 50Ω to V
CC
)
R
L
= 50Ω to V
CC
640
85
800
100
V
CC
-
0.2
1000
115
mVp-p
Ω
V
2
_______________________________________________________________________________________
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX3877/MAX3878
THRESHOLD SETTING SPECIFICATION
(SDI±)
Differential Input Voltage Range
Input Threshold Adjustment
Range
THADJ Voltage Range
Threshold Control Linearity
Threshold Setting Accuracy
Figure 2
V
TH
= ±30mV to ±80mV
(Note 5, Figure 2)
Threshold Setting Stability
V
TH
= ±80mV to ±180mV
(Note 5, Figure 2)
Maximum Input Current (THADJ,
PHADJ)
Control voltage = 0.2V to 2.2V
-11.5
-10
+11.5
+10
µA
V
ID
V
TH
V
THADJ
Note 4
Figure 2
Figure 2
100
-180
0.2
-5
-27
-7.0
600
180
2.2
+5
+27
+7.0
mV
mVp-p
mV
V
%
mV
TTL INPUT/OUTPUT SPECIFICATION
(SIS, LREF,
LOL,
LOS)
TTL Input High Voltage
(SIS, LREF)
TTL Input Low Voltage
(SIS, LREF)
TTL Input Current
(SIS, LREF)
TTL Output High Voltage
(LOL>, LOS)
TTL Output Low Voltage
(LOL>, LOS)
V
OH
V
OL
I
OH
= +40µA
I
OL
= -2mA
V
IH
V
IL
-10
2.4
0.4
2.0
0.8
+10
V
V
µA
V
V
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.)
(Note 6)
PARAMETER
Serial Output Clock Rate
Clock-to-Q Delay
Jitter Peaking
Jitter Transfer Bandwidth
J
P
J
BW
(Figure 4)
f
≤
2MHz
1.1
110
SYMBOL
CONDITIONS
MIN
TYP
2.488
290
0.1
2.0
MAX
UNITS
Gbps
ps
dB
MHz
_______________________________________________________________________________________
3
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
MAX3877/MAX3878
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.)
(Note 6)
PARAMETER
SYMBOL
f = 70kHz
f = 100kHz (see “Jitter Tolerance” graph in
Typical Operating Characteristics)
f = 1MHz
f = 10MHz
Jitter Generation
Clock Output Edge Speed
Data Output Edge Speed
Tolerated Consecutive Identical
Digits
Input Return Loss (SDI±, SLBI±)
2.5GHz to 4.0GHz
PLL Acquisition Time
LOS Assert Time
LOS Deassert Time
Low-Frequency Cutoff for
DC-Cancellation Loop
HOLDOVER SPECIFICATION
VCO Frequency Drift Rate in the
Absence of Data
PHASE ADJUST SPECIFICATION
Minimum Phase Adjust Range
Phase Adjust Stability
(Note 7)
(Note 8)
-60
-8
+60
+8
ps
ps
df/dt
C
FIL
= 1µF
6.2
kHz/µs
C
PWD
= 0.1µF
14.5
14
1.65
4.0
10
ms
µs
µs
kHz
J
GEN
Jitter bandwidth = 12kHz to 20MHz
0.026
(20% to 80%)
(20% to 80%)
BER
≤
10
-10
100kHz to 2.5GHz
2000
17
dB
0.056
120
120
UIp-p
ps
ps
bits
0.41
0.36
CONDITIONS
MIN
TYP
3.18
2.75
UIp-p
0.67
0.45
0.003
0.006
UI
RMS
MAX
UNITS
Jitter Tolerance
Note 1:
At T
A
= -40°C, DC characteristics are guaranteed by design and characterization.
Note 2:
Excluding PECL output termination, CML outputs open.
Note 3:
Jitter specifications are guaranteed for this data input voltage range, measured by connecting THADJ to V
CC
. Guaranteed
by design and characterization.
Note 4:
Jitter specifications are guaranteed when input threshold is set to
≤
30% of the differential input swing. Measured with edge
speed
≤
150ps (Figure 3). Guaranteed by design and characterization.
Note 5:
Threshold setting stability is guaranteed by design and characterization.
Note 6:
AC characteristics are guaranteed by design and characterization.
Note 7:
Phase adjust is disabled when PHADJ is connected to V
CC
.
Note 8:
Phase adjust stability is guaranteed over temperature and power-supply variation.
4
_______________________________________________________________________________________
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
MAX3877/MAX3878
SDI+
SDI-
5mV MIN
600mV MAX
(SDI+) -
(SDI-)
V
ID
10mVp-p MIN
1200mVp-p MAX
Figure 1. Input Amplitude
V
TH
(mV)
+207
+180
-153
THRESHOLD SETTING ACCURACY
(PART-TO-PART VARIATION OVER PROCESS)
1.1
0.2
1.3
2.2
THADJ (V)
-153
-180
-207
THRESHOLD SETTING STABILITY
(OVER TEMPERATURE OR SUPPLY)
Figure 2. Setting the Input Threshold Level
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