19-1467; Rev 2; 12/05
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
The MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
♦
Single +3.3V Supply
♦
910mW Operating Power
♦
Fully Integrated Clock Recovery and Data
Retiming
♦
Exceeds ANSI, ITU, and Bellcore Specifications
♦
Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
♦
2.488Gbps Serial to 155Mbps Parallel Conversion
♦
LVDS Data Outputs and Synchronization Inputs
♦
Tolerates >2000 Consecutive Identical Digits
♦
Loss-of-Lock Indicator
Features
MAX3880
Ordering Information
PART
MAX3880ECB
MAX3880ECB+
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
64 TQFP-EP*
64 TQFP-EP*
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
*Exposed
pad
+Denotes
lead-free package.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
0.01µF
+3.3V
V
CC
FIL
IN+
OUT+
SDI+
PD0+
PD15-
PHADJ+
PHADJ-
V
CC
PD15+
100Ω*
V
CC
MAX3866
PRE/POSTAMPLIFIER
OUT-
LOP
SDI-
MAX3880
PD0-
PCLK+
SLBI-
100Ω*
OVERHEAD
TERMINATION
100Ω*
PCLK-
SYNC+
TTL
SLBI+
SIS
SYSTEM
LOOPBACK
FIL+
FIL-
C
F
1µF
GND
LOL SYNC-
TTL
TTL
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z
0
= 50Ω.
________________________________________________________________
Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
MAX3880
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V
CC
)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-, SLBI+, SLBI-,
SYNC+, SYNC-)........................... (V
CC
- 0.5V) to (V
CC
+ 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at
LOL,
SIS, PHADJ+, PHADJ-,
FIL+, FIL- .................................................-0.5V to (V
CC
+ 0.5V)
Output Current LVDS Outputs ............................................10mA
Continuous Power Dissipation (T
A
= +85°C)
TQFP (derate 33.3mW/°C above +85°C) .......................1.44W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω ±1%, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
Supply Current
Differential Input Voltage
Single-Ended Input Voltage
Input Termination to Vcc
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of
Differential Output Voltage for
Complementary States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for
Complementary States
Single-Ended Output
Resistance
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage
Output Low Voltage
2
V
OH
V
OL
SYMBOL
I
CC
V
ID
V
IS
R
IN
V
I
V
IDTH
V
HYST
R
IN
V
OH
V
OL
0.925
Figure 2
250
400
±25
1.125
1.275
±25
85
Differential input voltage = 100mV
Common-mode voltage = 50mV
0
-100
78
100
115
1.475
Figure 1
50
V
CC
- 0.4
50
2.4
100
CONDITIONS
MIN
TYP
275
MAX
380
800
V
CC
+ 0.2
UNITS
mA
mVp-p
V
Ω
V
mV
mV
Ω
V
V
mV
mV
V
mV
SERIAL DATA INPUTS (SDI±, SLBI±)
LVDS INPUTS AND OUTPUTS (SYNC±, PCLK±, PD_±)
|
V
OD
|
∆|
V
OD
|
V
OS
∆
V
OS
R
O
40
95
140
Ω
∆
R
O
±2.5
±10
%
TTL INPUTS AND OUTPUTS (SIS,
LOL)
V
IH
V
IL
-10
2.4
2.0
0.8
+10
V
CC
0.4
V
V
µA
V
V
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω ±1%, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Serial Data Rate
Parallel Output Data Rate
Parallel Clock-to-Data Output
Delay
t
CLK-Q
Figure 5
f = 70kHz (Note 2)
Jitter Tolerance
f = 100kHz
f = 1MHz
f = 10MHz
Tolerated Consecutive Identical
Digits
Input Return Loss (SDI±, SLBI±)
100kHz to 2.5GHz
2.5GHz to 4.0GHz
200
2.31
1.74
0.38
0.28
SYMBOL
SDI
CONDITIONS
MIN
TYP
2.488
155.52
450
3.3
2.41
0.57
0.46
>2,000
-18
-11
Bits
dB
UIp-p
900
MAX
UNITS
Gbps
Mbps
ps
MAX3880
Note 1:
AC characteristics are guaranteed by design and characterization.
Note 2:
At jitter frequencies <70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. The low-frequency
jitter tolerance outperforms the instrument’s measurement capability.
SDI+
SDI-
25mV MIN
400mV MAX
(SDI+) - (SDI-)
V
ID
50mVp-p MIN
800mVp-p MAX
Figure 1. Input Amplitude
PD+
D
PD-
V
PD-
SINGLE-ENDED OUTPUT
V
PD+
V
OH
R
L
= 100Ω
V
V
OD
|
V
OD
|
V
OS
V
OL
V
PD+
- V
PD-
DIFFERENTIAL OUTPUT
0V (DIFF)
0V
+V
OD
V
OD, p-p
= V
PD+
- V
PD-
-V
OD
Figure 2. Driver Output Levels
_______________________________________________________________________________________
3
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
MAX3880
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
MAX3880-01
SUPPLY CURRENT vs. TEMPERATURE
MAX3880-02
JITTER TOLERANCE
MAX3880-03
300
290
SUPPLY CURRENT (mA)
280
270
V
CC
= 3.0V
260
250
240
V
CC
= 3.6V
10
DATA
2
23
- 1 PATTERN
INPUT JITTER (UIPp-p)
75
100
1
CLOCK
0.1
-50
-25
0
25
50
10
100
1,000
10,000
TEMPERATURE (°C)
JITTER FREQUENCY (kHz)
1.64ns/div
JITTER TOLERANCE vs. INPUT VOLTAGE
MAX3880-04
BIT ERROR RATE vs. INPUT VOLTAGE
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
MAX3880-05
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
MAX3880-06
0.8
0.7
JITTER TOLERANCE (UIp-p)
0.6
0.5
0.4
0.3
0.2
0.1
0
10
100
INPUT VOLTAGE (mVp-p)
SONET SPEC
JITTER FREQUENCY
= 5MHz
JITTER FREQUENCY = 1MHz
10
-3
10
-4
10
-5
BIT ERROR RATE
10
-6
10
-7
10
-8
10
-9
10
-10
700
600
500
400
300
200
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
1,000
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5 10.0
INPUT VOLTAGE (mVp-p)
4
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
1, 17, 25, 33,
41, 49, 56,
62, 64
2
3
4, 7, 10, 13,
24, 32, 40,
48, 57
5
6
8
9
11
12
14
15
16
18
19
20, 22, 26,
28, 30, 34,
36, 38, 42,
44, 46, 50,
52, 54, 58, 60
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
63
EP
NAME
GND
FIL+
FIL-
V
CC
Ground
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Negative Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Positive Synchronizing Pulse LVDS Input. Pulse the SYNC signal high for at least four serial-data
bit periods (1.6ns) to shift the data alignment by dropping 1 bit.
Negative Parallel Clock LVDS Output
Positive Parallel Clock LVDS Output
FUNCTION
MAX3880
PHADJ+
PHADJ-
SDI+
SDI-
SLBI+
SLBI-
SIS
SYNC-
SYNC+
PCLK-
PCLK+
PD0- to
PD15-
Negative Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
PD0+ to
PD15+
Positive Parallel Data LVDS Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 5).
LOL
Exposed Pad
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pull-up resistor). The
LOL
monitor is valid only when a data stream is present on the inputs to the MAX3880.
Ground. This must be soldered to a circuit board for proper thermal performance (see
Package
Information).
_______________________________________________________________________________________
5
单片机
