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Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
_______________General Description
The MAX509/MAX510 are quad, serial-input, 8-bit volt-
age-output digital-to-analog converters (DACs). They
operate with a single +5V supply or dual ±5V supplies.
Internal, precision buffers swing rail-to-rail. The refer-
ence input range includes both supply rails.
The MAX509 has four separate reference inputs, allow-
ing each DAC's full-scale range to be set independently.
20-pin DIP, SSOP, and SO packages are available. The
MAX510 is identical to the MAX509 except it has two ref-
erence inputs, each shared by two DACs. The MAX510
is housed in space-saving 16-pin DIP and SO packages.
The serial interface is double-buffered: A 12-bit input
shift register is followed by four 8-bit buffer registers and
four 8-bit DAC registers. A 12-bit serial word is used to
load data into each register. Both input and DAC regis-
ters can be updated independently or simultaneously
with single software commands. Two additional asyn-
chronous control pins provide simultaneous updating
(LDAC) or clearing (CLR) of input and DAC registers.
The interface is compatible with Microwire
TM
and SPI/
QSPI
TM
. All digital inputs and outputs are TTL/CMOS
compatible. A buffered data output provides for read-
back or daisy-chaining of serial devices.
____________________________Features
o
o
o
o
o
Single +5V or Dual ±5V Supply Operation
Output Buffer Amplifiers Swing Rail-to-Rail
Reference Input Range Includes Both Supply Rails
Calibrated Offset, Gain, and Linearity (1LSB TUE)
10MHz Serial Interface, Compatible with SPI, QSPI
(CPOL = CPHA = 0) and Microwire
o
Double-Buffered Registers for Synchronous
Updating
o
Serial Data Output for Daisy-Chaining
o
Power-On Reset Clears Serial Interface and Sets
All Registers to Zero
MAX509/MAX510
______________Ordering Information
PART
MAX509ACPP
MAX509BCPP
MAX509ACWP
MAX509BCWP
MAX509ACAP
MAX509BCAP
MAX509BC/D
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
20 Plastic DIP
20 Plastic DIP
20 Wide SO
20 Wide SO
20 SSOP
20 SSOP
Dice*
TUE
(LSB)
±1
±1 1/2
±1
±1 1/2
±1
±1 1/2
±1 1/2
_______________Functional Diagrams
CLR
DOUT
LDAC AGND DGND V
SS
V
DD
REFB
DECODE
CONTROL
REFA
Ordering Information continued on last page.
* Dice are specified at +25°C, DC parameters only.
**Contact factory for availability and processing to MIL-STD-883.
_________________Pin Configurations
OUTA
MAX509
TOP VIEW
OUTB
1
OUTA
2
OUTB
20
OUTC
19
OUTD
18
V
DD
INPUT
REG A
DAC
REG A
DAC A
12-BIT
SHIFT
REGISTER
INPUT
REG B
DAC
REG B
DAC B
V
SS
3
REFB
4
MAX509
17
REFC
16
REFD
15
CS
14
N.C.
13
SCLK
12
DIN
11
CLR
OUTC
INPUT
REG C
DAC
REG C
DAC C
REFA
5
AGND
6
N.C.
7
OUTD
SR
CONTROL
INPUT
REG D
DAC
REG D
DAC D
DGND
8
LDAC
9
DOUT
10
CS DIN SCLK
REFC
REFD
Functional Diagrams continued at end of data sheet.
DIP/SO/SSOP
Pin Configurations continued at end of data sheet.
Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
MAX509/MAX510
ABSOLUTE MAXIMUM RATINGS
V
DD
to DGND ..............................................................-0.3V, +6V
V
DD
to AGND...............................................................-0.3V, +6V
V
SS
to DGND ...............................................................-6V, +0.3V
V
SS
to AGND ...............................................................-6V, +0.3V
V
DD
to V
SS
.................................................................-0.3V, +12V
Digital Input Voltage to DGND ......................-0.3V, (V
DD
+ 0.3V)
REF_....................................................(V
SS
- 0.3V), (V
DD
+ 0.3V)
OUT_..............................................................................V
DD
, V
SS
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) ....842mW
16-Pin Wide SO (derate 9.52mW/°C above +70°C) .........762mW
16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW
20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW
20-Pin Wide SO (derate 10.00mW/°C above +70°C) .......800mW
20-Pin SSOP (derate 10.00mW/°C above +70°C) ............800mW
20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW
Operating Temperature Ranges:
MAX5_ _ _C_ _ .....................................................0°C to +70°C
MAX5_ _ _E_ _ ..................................................-40°C to +85°C
MAX5_ _ _MJ_ ................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note:
The outputs may be shorted to VDD, VSS, or AGND if the package power dissipation is not exceeded. Typical short-circuit current
to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
STATIC ACCURACY
Resolution
VREF = +4V,
VSS = 0V or -5V ±10%
VREF = -4V,
VSS = -5V ±10%
Guaranteed monotonic
Code = 00 hex,
VSS = 0V
Zero-Code Error
ZCE
Code = 00 hex,
VSS = -5V ±10%
Zero-Code-Error Supply Rejection
Zero-Code
Temperature Coefficient
Full-Scale Error
Full-Scale-Error Supply Rejection
Full-Scale-Error
Temperature Coefficient
MAX5_ _C
MAX5_ _E
MAX5_ _M
MAX5_ _C
MAX5_ _E
MAX5_ _M
1
±10
±14
MAX5_ _C
MAX5_ _E
MAX5_ _M
1
1
1
±10
4
8
12
µV/°C
mV
MAX5_ _A
MAX5_ _B
MAX5_ _A
MAX5_ _B
8
±1
±1.5
±1
±1.5
±1
14
16
20
±14
±16
±20
2
mV
µV/°C
mV
mV
LSB
LSB
Bits
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Total Unadjusted Error
TUE
Differential Nonlinearity
DNL
Code = 00 hex, V
DD
= 5V ±10%,
V
SS
= 0V or -5V ±10%
Code = 00 hex
Code = FF hex
Code = FF hex,
V
DD
= +5V ±10%,
V
SS
= 0V or -5V ±10%
Code = FF hex
2
_______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
REFERENCE INPUTS
Input Voltage Range
Input Resistance (Note 1)
Input Capacitance (Note 2)
Channel-to-Channel Isolation
AC Feedthrough
DAC OUTPUTS
Full-Scale Output Voltage
VREF = 4V, load regulation
≤
1/4LSB
VREF = -4V, V
SS
= -5V ±10%,
load regulation
≤
1/4LSB
Resistive Load
VREF = V
DD
MAX5_ _C/E,
load regulation
≤
1LSB
VREF = V
DD
MAX5_ _M,
load regulation
≤
2LSB
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
DYNAMIC PERFORMANCE
MAX5_ _C
Voltage-Output Slew Rate
Output Settling Time (Note 6)
Digital Feedthrough
Digital-to-Analog Glitch Impulse
Signal-to-Noise + Distortion Ratio
Multiplying Bandwidth
Wideband Amplifier Noise
SINAD
Positive and negative
MAX5_ _E
MAX5_ _M
To 1/2LSB, 10kΩ II 100pF load
Code = 00 hex, all digital inputs
from 0V to V
DD
Code 128¨127
VREF = 4V
p-p
at 1kHz, V
DD
= 5V,
code = FF hex
VREF = 4V
p-p
at 20kHz, V
SS
= -5V ±10%
VREF = 0.5V
p-p
, 3dB bandwidth
1.0
0.7
0.5
6
5
12
87
74
1
60
MHz
µV
RMS
µs
nV-s
nV-s
dB
V/µs
V
OH
V
OL
I
SOURCE
= 0.2mA
I
SINK
= 1.6mA
V
DD
- 0.5
0.4
V
V
V
IH
V
IL
I
IN
C
IN
V
IN
= 0V or V
DD
(Note 5)
2.4
0.8
1.0
10
V
V
µA
pF
V
SS
2
2
10
10
kΩ
V
DD
V
Code = 55 hex
Code = 00 hex
(Note 3)
(Note 4)
MAX509
MAX510
MAX509
MAX510
V
SS
16
8
24
12
15
30
-60
-70
V
DD
V
kΩ
pF
dB
dB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX509/MAX510
3
_______________________________________________________________________________________
Quad, Serial 8-Bit DACs
with Rail-to-Rail Outputs
MAX509/MAX510
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V ±10%, VSS = 0V to -5.5V, VREF = 4V, AGND = DGND = 0V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX,
unless otherwise noted.)
PARAMETER
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
SYMBOL
V
DD
V
SS
I
DD
I
SS
CONDITIONS
For specified performance
For specified performance
Outputs unloaded, all
digital inputs = 0V or V
DD
V
SS
= -5V ±10%, outputs
unloaded, all digital
inputs = 0V or V
DD
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MIN
4.5
-5.5
5
5
5
5
TYP
MAX
5.5
0
10
12
10
12
UNITS
V
V
mA
mA
Note 1:
Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2:
Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3:
VREF = 4V
p-p
, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 4:
VREF = 4V
p-p
, 10kHz. DAC code = 00 hex.
Note 5:
Guaranteed by design.
Note 6:
Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
TIMING CHARACTERISTICS
(VDD = +5V ±10%, VSS = 0V to -5V, VREF = 4V, AGND = DGND = 0V, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
LDAC
Pulse Width Low
CS
Rise to
LDAC
Fall Setup Time
CLR
Pulse Width Low
SERIAL INTERFACE TIMING
CS
Fall to SCLK Setup Time
SCLK Fall to
CS
Rise Hold Time
SCLK Rise to
CS
Rise Hold Time
SCLK Fall to
CS
Fall Hold Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Clock Frequency
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK to DOUT Valid
t
CSS
t
CSH2
t
CSH1
t
CSH0
t
DS
t
DH
f
CLK
t
CH
t
CL
t
DO
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
(Note 9)
(Note 7)
MAX5_ _C/E
MAX5_ _M
40
50
0
40
0
40
50
0
20
20
40
50
40
50
10
10
12.5
10
ns
ns
ns
ns
ns
ns
MHz
ns
ns
100
100
ns
SYMBOL
t
LDW
t
CLL
t
CLW
MAX5_ _C/E
MAX5_ _M
(Notes 7, 8)
MAX5_ _C/E
MAX5_ _M
CONDITIONS
MIN
40
50
0
40
50
TYP
20
25
20
25
MAX
UNITS
ns
ns
ns
Note 7:
Guaranteed by design.
Note 8:
If
LDAC
is activated prior to
CS's
rising edge, it must stay low for t
LDW
or longer after
CS
goes high.
Note 9:
Minimum delay from 12th clock cycle to
CS
rise.
4
_______________________________________________________________________________________
