MB3793-42
Power-Voltage Monitoring IC with
Watchdog Timer
Description
The MB3793 is an integrated circuit to monitor power voltage; it incorporates a watchdog timer.
A reset signal is output when the power is cut or falls abruptly. When the power recovers normally after resetting, a power-on reset
signal is output to microprocessor units (MPUs). An internal watchdog timer with two inputs for system operation diagnosis can provide
a fail-safe function for various application systems.
The model number and package code are as shown below.
Model No.
MB3793-42
Marking Code
3793-A
Detection Voltage
4.2 V
Features
■
■
■
■
■
■
■
■
Precise detection of power voltage fall:
±2.5%
Detection voltage with hysteresis
Low power dispersion: I
CC
= 27
μA
(reference)
Internal dual-input watchdog timer
Watchdog timer halt function (by inhibition terminal)
Independently-set watchdog and reset times
Mask option for detection voltage (4.9 to 2.4 V, 0.1-V steps)
Two types of packages (SOP-8pin: 2 types)
Application
■
Arcade Amusement etc.
Cypress Semiconductor Corporation
Document Number: 002-08515 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 28, 2017
MB3793-42
Contents
Description ...............................................................1
Features ...................................................................1
Application ...............................................................1
1. PIN ASSIGNMENT ..............................................3
2. PIN DESCRIPTION ..............................................3
3. BLOCK DIAGRAM ..............................................4
4. BLOCK FUNCTIONS ...........................................5
5. ABSOLUTE MAXIMUM RATINGS ......................6
6. RECOMMENDED OPERATING CONDITIONS ..6
7. ELECTRICAL CHARACTERISTICS ...................7
7.1 DC Characteristics .......................................7
7.2 AC Characteristics .......................................8
8. TIMING DIAGRAM ...............................................9
8.1 Basic operation (Positive clock pulse) ........9
8.2 Basic operation (Negative clock pulse) ......10
8.3 Single-clock input monitoring (Positive clock
pulse) ................................................................11
8.4 Inhibition operation (Positive clock pulse) ..12
8.5 Clock pulse input (Positive clock pulse) .....13
8.6 Inhibition input rising and falling time .........13
9. OPERATION SEQUENCE .................................14
10. TYPICAL CHARACTERISTICS ......................15
11. STANDARD CONNECTION ............................18
12. APPLICATION EXAMPLE ..............................19
12.1 Monitoring Single Clock ...........................19
12.2 Watchdog Timer Stopping .......................19
13. NOTES ON USE ..............................................20
14. ORDERING INFORMATION ...........................20
15. ROHS COMPLIANCE INFORMATION ...........20
16. PACKAGE DIMENSIONS ...............................21
17. MAJOR CHANGES .........................................23
Document History .................................................23
Sales, Solutions, and Legal Information .............24
Document Number: 002-08515 Rev. *C
Page 2 of 24
MB3793-42
1. Pin Assignment
(TOP VIEW)
RESET
CTW
CTP
GND
1
2
3
4
(
SOE008
)
(
SOB008
)
8
7
6
5
CK1
CK2
INH
V
CC
2. Pin Description
Pin No.
1
2
3
4
Symbol
RESET
CTW
CTP
GND
Description
Outputs reset
Sets monitoring time
Sets power-on reset hold time
Ground
Pin No.
5
6
7
8
Symbol
V
CC
INH
CK2
CK1
Description
Power supply
Inhibits watchdog timer function
Inputs clock 2
Inputs clock 1
Document Number: 002-08515 Rev. *C
Page 3 of 24
MB3793-42
3. Block Diagram
To V
CC
of all blocks
5
I
1
≅
3
μA
I
2
≅
30
μA
V
CC
CTP
3
Q
S
R
1
≅
590 kΩ
Output
buffer
Comp. O
+
RSFF2
Q
R
RESET
1
−
Q
S
RSFF1
Q
INH
6
R
Comp. S
CTW
2
Watchdog
timer
Pulse generator 1
Reference
voltage
generator
V
REF
≅
1.24 V
−
+
V
S
CK1
8
R
2
≅
240 kΩ
Pulse generator 2
CK2
7
To GND of all blocks
4
GND
Document Number: 002-08515 Rev. *C
Page 4 of 24
MB3793-42
4. Block Functions
1. Comp. S
Comp. S is a comparator with hysteresis to compare the reference voltage with a voltage (V
S
) that is the result of dividing the power
voltage (V
CC
) by resistors R
1
and R
2
. When V
S
falls below 1.24 V, a reset signal is output. This function enables the MB3793 to detect
an abnormality within 1
μs
when the power is cut or falls abruptly.
2. Comp. O
Comp. O is a comparator to control the reset signal (RESET) output and compares the threshold voltage with the voltage at the CTP
terminal for setting the power-on reset hold time. When the voltage at the CTP terminal exceeds the threshold voltage, resetting is
canceled.
3. Reset Output Buffer
Since the reset (RESET) output buffer has CMOS organization, no pull-up resistor is needed.
4. Pulse Generator
The pulse generator generates pulses when the voltage at the CK1 and CK2 input clock terminals changes to High from Low level
(positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog timer.
5. Watchdog Timer
The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock terminals to monitor a single clock pulse.
6. Inhibition Terminal
The inhibition (INH) terminal forces the watchdog timer on/off. When this terminal is High level, the watchdog timer is stopped.
7. Flip-flop Circuit
The flip-flop circuit RSFF1 controls charging and discharging of the power-on reset hold time setting capacity (C
TP
). The flip-flop circuit
RSFF2 switches the charging accelerator for charging C
TP
during resetting on/off. This circuit only functions during resetting and does
not function at power-on reset.
Document Number: 002-08515 Rev. *C
Page 5 of 24
