FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27235-2E
ASSP For Power Supply Applications
(General Purpose DC/DC Converter)
2-Channel DC/DC Converter IC
with Overcurrent Protection Symmetrical-Phase Type
MB39A106
■
DESCRIPTION
The MB39A106 is a symmetrical-phase type of two-channel, DC/DC converter IC using pulse width modulation
(PWM) , incorporating an overcurrent protection circuit (requiring no current sense resistor) and an overvoltage
protection circuit. Providing high output driving capabilities, the MB39A106 is suitable for down-conversion.
The MB39A106 adopts both synchronous rectification to provide high efficiency and symmetrical phasing (two
anti-phase triangular waves) which contributes to making the input capacitor small.
The MB39A106 contains a Bootstrap diode resulting in a reduced number of components used. It also contains
a variety of protection features which output the protection status upon detection of an overvoltage or overcurrent
while reducing the number of external protective devices required.
The result is an ideal built-in power supply for driving products with high speed CPU’s such as home TV game
devices and notebook PC’s.
■
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Built-in bootstrap diode
Built-in timer-latch overcurrent protection circuit (requiring no current sense resistor)
Built-in timer-latch overvoltage protection circuit
Synchronous rectification system providing high efficiency
Power supply voltage range: 6.5 V to 18 V
PWRGOOD terminals (open-drain) to output the protection status
Symmetrical-phase system reducing the input capacitor loss
Built-in channel control function
One type of package (TSSOP-30pin : 1 type)
Reference voltage: 3.5 V
±
1
%
Error amplifier threshold voltage: 1.23 V
±
1
%
(Ta
=
0
°C
to
+
85
°C)
Support for frequency setting using an external resistor (Frequency setting capacitor integrated)
Oscillation frequency range: 100 kHz to 500 kHz
Standby current : 0
µA
(Typ)
Built-in circuit for load-independent soft-start and discharge control
Built-in totem-pole output for N-ch MOS FET
One type of package (TSSOP-30 pin : 1 type)
■
APPLICATION
• Home Video Game
• IP phone
• Printer
etc.
Copyright©2002-2006 FUJITSU LIMITED All rights reserved
MB39A106
■
PIN ASSIGNMENT
(TOP VIEW)
−INE1
: 1
FB1 : 2
CS1 : 3
NC : 4
RT : 5
CTL : 6
SGND : 7
VREF : 8
CTL1 : 9
CTL2 : 10
CSCP : 11
PWRGOOD : 12
CS2 : 13
FB2 : 14
−INE2
: 15
30 : CB1
29 : OUT1-1
28 : VS1
27 : OUT2-1
26 : PGND1
25 : ILIM1
24 : VCC
23 : ILIM2
22 : VB
21 : NC
20 : PGND2
19 : OUT2-2
18 : VS2
17 : OUT1-2
16 : CB2
(FPT-30P-M04)
2
MB39A106
■
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
Symbol
−INE1
FB1
CS1
NC
RT
CTL
SGND
VREF
CTL1
I/O
I
O
⎯
⎯
⎯
I
⎯
O
I
CH1 error amp output terminal
CH1 soft-start capacitor connection terminal
No connection
Triangular waveform oscillation frequency setting resistor connection
terminal
Power supply control terminal
“H” level : IC operating mode
“L” level : IC Standby mode
Ground terminal
Reference voltage output terminal
CH1 control terminal
“H” level : CH1 ON state
“L” level : CH1 OFF state and protection status reset
CH2 control terminal
“H” level : CH2 ON state
“L” level : CH2 OFF state and protection status reset
Timer-latch short-circuit protection capacitor connection terminal
CH1, CH2 protection status output terminal
CH2 soft-start capacitor connection terminal
CH2 error amp output terminal
CH2 error amp inverted input terminal
CH2 boot capacitor connection terminal
Connect a capacitor between the CB2 and VS2 terminals.
CH2 totem-pole output terminal (External main-side FET gate drive)
CH2 external main-side FET source connection terminal
CH2 totem-pole output terminal (External synchronous-rectification-side FET
gate drive)
Ground terminal
No connection
Output circuit bias output terminal
CH2 overcurrent detection resistor connection terminal
Reference voltage, control circuit power supply terminal
CH1 overcurrent detection resistor connection terminal
Ground terminal
CH1 totem-pole output terminal (External synchronous-rectification-side FET
gate drive)
CH1 external main-side FET source connection terminal
CH1 totem-pole output terminal (External main-side FET gate drive)
CH1 boot capacitor connection terminal
Connect a capacitor between the CB1 and VS1 terminals.
3
Descriptions
CH1 error amp inverted input terminal
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CTL2
CSCP
PWRGOOD
CS2
FB2
−INE2
CB2
OUT1-2
VS2
OUT2-2
PGND2
NC
VB
ILIM2
VCC
ILIM1
PGND1
OUT2-1
VS1
OUT1-1
CB1
I
⎯
O
⎯
O
I
⎯
O
⎯
O
⎯
⎯
O
I
⎯
I
⎯
O
⎯
O
⎯
MB39A106
■
BLOCK DIAGRAM
VCC
24
6V
VB Reg.
FB1 2
L priority
L priority
22 VB
CH1
Dead Time
Modulation 1
PWM
+
Comp.1
+
−
Max Duty 81%
Dtr
±
6%
30 CB1
Drv
1-1
29 OUT1-1
28 VS1
Drv
2-1
27 OUT2-1
26 PGND1
Current
Protection
Logic
H: at OCP
−
+
118
µA
25 ILIM1
−INE1
1
CS1
3
VREF 3
µA
100
kΩ
Buff
CTL1
9
Open : CH1 ON
CTL1
=
H
L : CH1 OFF
6 kΩ
VTH
=
1.4 V
−
+
+
1.23 V
OVP
+
Comp.1
−
1.38 V
Error
Amp1
FB2 14
L priority
L priority
−INE2
15
CS2
13
VREF 3
µA
100
kΩ
Buff
CTL2
10
Open : CH2 ON
CTL2
=
H
L : CH2 OFF
6 kΩ
VTH
=
1.4 V
Error
Amp2
−
+
+
1.23 V
OVP
+
Comp.2
−
1.38 V
Dead Time
Modulation 2
PWM
Comp.2
+
+
−
Max Duty 81%
Dtr
±
6%
CH2
16 CB2
Drv
1-2
17 OUT1-2
18 VS2
Drv
2-2
OCP
Comp.2
−
+
118
µA
19 OUT2-2
20 PGND2
Current
Protection
Logic
H: at OCP
23 ILIM2
H: priority
SCP Comp.
+
+
−
H: at OVP
H: at
UVLO release
3.1 V
H: at OVP
H: at OVP
H: at OCP
H: at SCP
Latch1
SQ
L: at protection
operation
CTL
CTL1
CTL2
10
µA
CTL
CTL1
CTL2
S R
Latch
Latch2
R
PWRGOOD
12
Protection
control
signal
CSCP 11
VREF
UVLO
OSC
45 pF
3.0 V
CT1
1.8 V
3.0 V
CT2
1.8 V
4 NC
to Error amp reference
1.23 V
bias
VREF
3.5 V
VCC
21 NC
6 CTL
Power
VR1 ON/OFF
CTL
7
SGND
5
RT
8
VREF
H : ON (Power On)
L : OFF (Standby mode)
VTH
=
1.4 V
4
MB39A106
■
ABSOLUTE MAXIMUM RATINGS
Parameter
Power-supply voltage
Boot voltage
Output current
Peak output current
Power dissipation
Storage temperature
Symbol
V
CC
V
CB
I
O
I
OP
P
D
T
STG
Condition
⎯
CB terminal
⎯
Duty
≤
5%
(t
=
1 / f
OSC
×
Duty)
Ta
≤ +25 °C
⎯
Rating
Min
⎯
⎯
⎯
⎯
⎯
−55
Max
20
25
120
800
1390*
+125
Unit
V
V
mA
mA
mW
°C
* : The packages are mounted on the dual-sided epoxy board (10 cm
×
10 cm) .
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
5