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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-11303-4E

MEMORY

CMOS

1 M

16 BIT

HYPER PAGE MODE DYNAMIC RAM

MB81V16165B-50/-60/-50L/-60L

CMOS 1,048,576

16 Bit Hyper Page Mode Dynamic RAM

DESCRIPTION

The Fujitsu MB81V16165B is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory

cells accessible in 16-bit increments. The MB81V16165B features a “hyper page” mode of operation whereby

high-speed random access of up to 256

16 bits of data within the same row can be selected. The MB81V16165B

DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory

applications where very low power dissipation and high bandwidth are basic requirements of the design. Since

the standby current of the MB8118165B is very small, the device can be used as a non-volatile memory in

equipment that uses batteries for primary and/or auxiliary power.

The MB81V16165B is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-

layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the

possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for

the MB81V16165B are not critical and all inputs are LVTTL compatible.

PRODUCT LINE & FEATURES

Parameter

RAS Access Time

Random Cycle Time

Address Access Time

CAS Access Time

Hyper Page Mode Cycle Time

Operating Current

Low Power

Dissipation

Standby

Current

LVTTL level

CMOS level

MB81V16165B

-50

50 ns max.

84 ns min.

25 ns max.

13 ns max.

20 ns min.

432 mW max.

3.6 mW max.

1.8 mW max.

3.6 mW max.

0.54 mW max.

-50L

-60

60 ns max.

104 ns min.

30 ns max.

15 ns max.

25 ns min.

360 mW max.

3.6 mW max.

1.8 mW max.

3.6 mW max.

0.54 mW max.

-60L

• 1,048,576 words

16 bits organization

• Silicon gate, CMOS, Advanced Stacked

Capacitor Cell

• All input and output are LVTTL compatible

• 4,096 refresh cycles every 32.8 ms

• Self refresh function (Low power version)

• Early write or OE controlled write capability

• RAS-only, CAS-before-RAS, or Hidden

Refresh

• Hyper Page Mode, Read-Modify-Write

capability

• On chip substrate bias generator for high

performance

• Standard and low power versions

MB81V16165B-50/-60/-50L/-60L

PACKAGE

42-pin plastic SOJ

50-pin plastic TSOP (II)

(LCC-42P-M01)

(FPT-50P-M06)

(Normal Bend)

Package and Ordering Information

– 42-pin plastic (400mil) SOJ, order as MB81V16165B-××PJ

– 50-pin plastic (400mil) TSOP(II) with normal bend leads, order as MB81V16165B-××PFTN

and MB81V16165B-××LPFTN (Low Power)

MB81V16165B-50/-60/-50L/-60L

PIN ASSIGNMENTS AND DESCRIPTIONS

42-Pin SOJ

(TOP VIEW)

<LCC-42P-M01>

N.C.

RAS

1 Pin Index 40

N.C.

LCAS

UCAS

Designator

to A

Function

Address inputs

row

: A

to A

column : A

to A

refresh : A

to A

Row address strobe

Lower column address strobe

Upper column address strobe

Write enable

Output enable

Data Input/Output

+3.3 volt power supply

Circuit ground

No connection

RAS

LCAS

UCAS

to DQ

N.C.

50-Pin TSOP(II)

(TOP VIEW)

N.C.

1 Pin Index 48

N.C.

RAS

N.C.

LCAS

UCAS

MB81V16165B-50/-60/-50L/-60L

Fig. 1 – MB81V16165B DYNAMIC RAM - BLOCK DIAGRAM

RAS

UCAS

LCAS

Clock

Gen #1

Write

Clock

Gen

Mode

Control

Clock

Gen #2

Refresh

Address

Counter

Row

Decoder

16,777,216 Bit

Storage

Cell

Address

Buffer

Pre-

Decoder

Column

Decoder

Sense Amp &

I/O Gate

Data In

Buffer

Data Out

Buffer

Substrate

Bias Gen

MB81V16165B-50/-60/-50L/-60L

FUNCTIONAL TRUTH TABLE

Clock Input

Operation

Mode

Standby

Read Cycle

Write Cycle

(Early Write)

Read-Modify-

Write Cycle

RAS-only

Refresh

Cycle

CAS-before-

RAS Refresh

Cycle

Hidden

Refresh

Cycle

RAS

LCAS UCAS

Address Input

Row Column

Input/Output Data

to DQ

Input

Output

to DQ

Refresh

Input

Output

Note

—

Valid

—

Valid

—

High-Z

Valid

High-Z

Valid

—

High-Z

Valid

—

Yes*

RCS

≥

RCS

(min)

WCS

≥

WCS

(min)

Valid

—

— High-Z Valid High-Z

Valid

— High-Z

Valid Valid

— High-Z Valid Valid

Valid Valid Valid Valid

—

High-Z

—

High-Z

Yes*

H→L L→H Valid

Valid

Yes*

Valid

Yes

CSR

≥

CSR

(min)

data is

kept

—

High-Z

Valid

High-Z

Valid

—

High-Z

Valid

Yes

H→L

H→X

—

Yes

X : “H” or “L”

* : It is impossible in Hyper Page Mode.

FUNCTIONAL OPERATION

ADDRESS INPUTS

Twenty input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. Since

only twelve address bits (A

to A

) are available, the column and row inputs are separately strobed by LCAS or

UCAS and RAS as shown in Figure 1. First, twelve row address bits are input on pins A

-through-A

and latched

with the row address strobe (RAS) then, eight column address bits are input and latched with the column address

strobe (LCAS or UCAS). Both row and column addresses must be stable on or before the falling edges of RAS

and LCAS or UCAS, respectively. The address latches are of the flow-through type; thus, address information

appearing after t

RAH

(min) + t

is automatically treated as the column address.

WRITE ENABLE

The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;

when WE is High, a read cycle is selected. During the read mode, input data is ignored.

DATA INPUTS

Input data is written into memory in either of three basic ways : an early write cycle, an OE (delayed) write cycle,

and a read-modify-write cycle. The falling edge of WE or LCAS / UCAS, whichever is later, serves as the input

data-latch strobe. In an early write cycle, the input data of DQ

to DQ

is strobed by LCAS and DQ

to DQ

strobed by UCAS and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low

before LCAS / UCAS. in a delayed write or a read-modify-write cycle, WE goes Low after LCAS / UCAS; thus,

input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.

参数对比

与MB81V16165B-60PFTN相近的元器件有：MB81V16165B-50PJ、MB81V16165B-60PJ、MB81V16165B-50LPFTN、MB81V16165B-60LPFTN、MB81V16165B-50PFTN。描述及对比如下：

型号	MB81V16165B-60PFTN	MB81V16165B-50PJ	MB81V16165B-60PJ	MB81V16165B-50LPFTN	MB81V16165B-60LPFTN	MB81V16165B-50PFTN
描述	EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-50/44	EDO DRAM, 1MX16, 50ns, CMOS, PDSO42, 0.400 INCH, PLASTIC, SOJ-42	EDO DRAM, 1MX16, 60ns, CMOS, PDSO42, 0.400 INCH, PLASTIC, SOJ-42	EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-50/44	EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-50/44	EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-50/44
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
包装说明	TSOP2, TSOP44/50,.46,32	SOJ, SOJ42,.44	SOJ, SOJ42,.44	0.400 INCH, PLASTIC, TSOP2-50/44	TSOP2, TSOP44/50,.46,32	0.400 INCH, PLASTIC, TSOP2-50/44
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FAST PAGE WITH EDO	FAST PAGE WITH EDO	FAST PAGE WITH EDO	FAST PAGE WITH EDO	FAST PAGE WITH EDO	FAST PAGE WITH EDO
最长访问时间	60 ns	50 ns	60 ns	50 ns	60 ns	50 ns
其他特性	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEELF REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEELF REFRESH	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PDSO-G44	R-PDSO-J42	R-PDSO-J42	R-PDSO-G44	R-PDSO-G44	R-PDSO-G44
JESD-609代码	e0	e0	e0	e0	e0	e0
长度	20.95 mm	27.3 mm	27.3 mm	20.95 mm	20.95 mm	20.95 mm
内存密度	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit
内存集成电路类型	EDO DRAM	EDO DRAM	EDO DRAM	EDO DRAM	EDO DRAM	EDO DRAM
内存宽度	16	16	16	16	16	16
功能数量	1	1	1	1	1	1
端口数量	1	1	1	1	1	1
端子数量	44	42	42	44	44	44
字数	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words	1048576 words
字数代码	1000000	1000000	1000000	1000000	1000000	1000000
工作模式	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	1MX16	1MX16	1MX16	1MX16	1MX16	1MX16
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	SOJ	SOJ	TSOP2	TSOP2	TSOP2
封装等效代码	TSOP44/50,.46,32	SOJ42,.44	SOJ42,.44	TSOP44/50,.46,32	TSOP44/50,.46,32	TSOP44/50,.46,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096	4096	4096	4096
座面最大高度	1.2 mm	3.75 mm	3.75 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	NO	NO	NO	YES	YES	NO
最大待机电流	0.0005 A	0.0005 A	0.0005 A	0.00015 A	0.00015 A	0.0005 A
最大压摆率	0.1 mA	0.12 mA	0.1 mA	0.12 mA	0.1 mA	0.12 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	J BEND	J BEND	GULL WING	GULL WING	GULL WING
端子节距	0.8 mm	1.27 mm	1.27 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
厂商名称	FUJITSU(富士通)	-	-	FUJITSU(富士通)	FUJITSU(富士通)	FUJITSU(富士通)
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	-	NOT SPECIFIED