FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50216-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (× 8/×16) FLASH MEMORY &
2M (× 8/×16) STATIC RAM
MB84VD2108XEA
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/MB84VD2109XEA
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s
FEATURES
• Power Supply Voltage of 2.7 to 3.3 V
• High Performance
70 ns maximum access time
• Operating Temperature
–40 to +85°C
• Package 56-ball FBGA, 56-pin TSOP
s
PRODUCT LINE UP
Flash Memory
-70
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f*
=
3.0 V
70
70
30
+0.3 V
–0.3 V
SRAM
-85
85
85
35
-70
V
CC
s*
=
3.0 V
70
70
35
+0.3 V
–0.3 V
-85
85
85
45
* : Both V
CC
f and V
CC
s must be in recommend operation range when either part is being accessed.
s
PACKAGES
56-ball plastic FBGA
56-pin plastic TSOP
(BGA-56P-M01)
(FPT-56P-M04)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VD2108XEA
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FLASH MEMORY
•
Simultaneous Read/Write Operations (dual bank)
Miltiple devices available with different bank sizes (refer to “s PIN DESCRIPTION”)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
•
Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•
Boot Code Sector Architecture
MB84VD2108XEA: Top sector
MB84VD2109XEA: Bottom sector
•
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
•
Low V
CC
Write Inhibit
≤
2.5 V
•
Hidden ROM (Hi-ROM) Region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC Input Pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2108XEA:SA37,SA38 MB84VD2109XEA:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
•
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” datasheet in detailed function
SRAM
•
Power Dissipation
Operating : 50 mA Max
Standby : 7
µA
Max
• Power Down Features Using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LBs (DQ
7
-DQ
0
), UBs (DQ
15
-DQ
8
)
2
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PIN ASSIGNMENTS
(TOP VIEW)
Marking side
B8
A15
C8
NC
D8
NC
E8
A16
F8
CIOf
G8
Vss
A7
A11
A6
A8
A5
WE
B7
A12
B6
A19
C7
A13
C6
A9
C5
NC
D7
A14
D6
A10
E7
SA
E6
DQ6
F7
DQ15/A-1
F6
DQ13
F5
DQ4
G7
DQ7
G6
DQ12
G5
Vccs
H7
DQ14
H6
DQ5
B5
CE2s
H5
CIOs
A4
WP/ACC
B4
RESET
C4
RY/BY
INDEX
LAND*
D3
A17
E3
DQ1
F4
DQ3
G4
Vccf
H4
DQ11
A3
LBs
B3
UBs
C3
A18
F3
DQ9
G3
DQ10
H3
DQ2
A2
A7
B2
A6
C2
A5
D2
A4
E2
Vss
F2
OE
G2
DQ0
H2
DQ8
B1
A3
C1
A2
D1
A1
E1
A0
F1
CEf
G1
CE1s
* : There is no solder ball. This land should be open electrically.
56-ball FBGA
(BGA-56P-M01)
(Continued)
3
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(Continued)
(Top View)
NC
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2S
RESET
WP/ACC
RY/BY
UBs
LBs
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A16
CIOf
VSS
SA
DQ15/A
–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
CIOs
VCCs
VCCf
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1s
CEf
A0
56-pin TSOP
(FPT-56P-M04)
4
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PIN DESCRIPTION
Pin
A
0
to A
16
A
–1
, A
17
to A
19
SA
DQ
0
to DQ
15
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
CIOf
CIOs
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
Address Input (Common)
Address Input (Flash)
Address Input (SRAM)
Data Input/Output (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configuration (Flash)
CIOf = V
CC
f is Word mode (×16), CIOf = V
SS
is Byte mode (×8)
I/O Configuration (SRAM)
CIOs = V
CC
s is Word mode (×16), CIOs = V
SS
is Byte mode (×8)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Function
Input/Output
I
I
I
I/O
I
I
I
I
I
O
I
I
I
I
I
I
—
Power
Power
Power
5
