FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50211-5E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (×8/×16) FLASH MEMORY &
8M (×8/×16) STATIC RAM
MB84VD23280EA
/
EE
-85
s
FEATURES
• Power Supply Voltage of 2.7 V to 3.3 V
• High Performance
85 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–25
°C
to +85
°C
• Package 101-ball BGA
(Continued)
s
PRODUCT LINEUP
Flash Memory
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f* = 3.0 V
85
85
35
+0.3V
–0.3 V
SRAM
V
CC
s* = 3.0 V
70
70
35
+0.3V
–0.3 V
*: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
PACKAGE
101-ball plastic FBGA
BGA-101P-M01
MB84VD23280EA/EE-85
(Continued)
— FLASH MEMORY
• Simultaneous Read/Write Operations (Flex Bank)
Two virtual Banks are chosen from the combination of four physical banks
Host system can program or erase in one bank, then read immediately and simultaneously read from the other
bank between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
• Sector Erase Architecture
Sixteen 4 K words and one hundred twenty-six 32 K word.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Embedded Erase
TM
* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic Sleep Mode
When addresses remain stable, the device automatically switches themselves to low power mode.
• Low V
CC
Write Inhibit
≤
2.5 V
• Hidden ROM (Hi-ROM) Region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide secure electronic serial number (ESN)
• WP/ACC Input Pin
At V
IL
, allows protection of 2 of 8 Kbytes on both ends of each boot sector, regardless of sector protection/
unprotection status.
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will be reduced by 40
%
• Program Suspend/Resume
Suspends the program operation to allow to read in another address
• Erase Suspend/Resume
Suspends the erase operation to allow to read in another sector within the same device
• Please refer to “MBM29DL640E” Datasheet in Detailed Function
— SRAM
• Power Dissipation
Operating : 50 mA Max
Standby : 15
µA
Max
• Power Down Features Using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LBs (DQ
7
-DQ
0
), UBs (DQ
15
-DQ
8
)
*: Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MB84VD23280EA/EE-85
s
PIN ASSIGNMENT
(TOP View)
Marking Side
A12
N.C.
A11
N.C.
A10
N.C.
B12
N.C.
B11
N.C.
B10
N.C.
C12
N.C.
C11
N.C.
C10
N.C.
D9
A
11
D8
A
8
C7
N.C.
C6
N.C.
D7
WE
D6
WP/ACC
D5
LBs
D4
A
7
E10
A
15
E9
A
12
E8
A
19
E7
CE2s
E6
RESET
E5
UBs
E4
A
6
E3
A
3
D2
N.C.
F10
A
21
F9
A
13
F8
A
9
F7
A
20
F6
RY/BY
F5
A
18
F4
A
5
F3
A
2
G5
A
17
G4
A
4
G3
A
1
G2
N.C.
H5
DQ
1
H4
Vss
H3
A
0
H2
N.C.
G11
N.C.
G10
N.C.
G9
A
14
G8
A
10
H11
N.C.
H10
A
16
H9
SA
H8
DQ
6
J10
CIOf
J9
DQ
15
/A
-1
J8
DQ
13
J7
DQ
4
J6
DQ
3
J5
DQ
9
J4
OE
J3
CEf
K10
Vss
K9
DQ
7
K8
DQ
12
K7
Vccs
K6
Vccf
K5
DQ
10
K4
DQ
0
K3
CE1s
L9
DQ
14
L8
DQ
5
L7
CIOs
L6
DQ
11
L5
DQ
2
L4
DQ
8
M12
N.C.
M11
N.C.
M10
N.C.
N12
N.C.
N11
N.C.
N10
N.C.
P12
N.C.
P11
N.C.
P10
N.C.
M7
N.C.
M6
N.C.
A3
N.C.
A2
N.C.
A1
N.C.
B3
N.C.
B2
N.C.
B1
N.C.
C3
N.C.
C2
N.C.
C1
N.C.
M3
N.C.
M2
N.C.
M1
N.C.
N3
N.C.
N2
N.C.
N1
N.C.
P3
N.C.
P2
N.C.
P1
N.C.
(BGA-101P-M01)
3
MB84VD23280EA/EE-85
s
PIN DESCRIPTION
Pin name
A
18
to A
0
A
21
to A
19
, A
–1
SA
DQ
15
to DQ
0
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
CIOf
CIOs
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
Input/
Output
I
I
I
I/O
I
I
I
I
I
O
I
I
I
I
I
I
—
Power
Power
Power
Address Inputs (Common)
Address Inputs (Flash)
Address Input (SRAM)
Data Inputs/Outputs (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Output (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configuration (Flash)
CIOf = V
CC
f is Word mode (×16), CIOf = V
SS
is Byte mode (×8)
I/O Configuration (SRAM)
CIOs = V
CC
s is Word mode (×16), CIOs = V
SS
is Byte mode (×8)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Description
4
MB84VD23280EA/EE-85
s
BLOCK DIAGRAM
V
CC
f
A
21
to A
0
A
21
to A
0
A
–1
WP/ACC
RESET
CEf
CIOf
V
SS
RY/BY
64 M bit
Flash Memory
DQ
15
/A
–
1
to DQ
0
DQ
15
/A
–
1
to DQ
0
V
CC
s
A
18
to A
0
DQ
15
to DQ
0
SA
LBs
UBs
WE
OE
CE1s
CE2s
CIOs
8 M bit
Static RAM
V
SS
5
PCB设计
