SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50221-2E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (×8/×16) FLASH MEMORY &
8M (×8/×16) STATIC RAM
MB84VD23280FA
-70
s
FEATURES
• Power supply voltage of 2.7 V to 3.1 V
•
High performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
•
Operating Temperature
–40
°
C to +85
°
C
• Package 65-ball FBGA
(Continued)
s
PRODUCT LINEUP
Flash Memory
Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
r* = 3.0 V
70
70
30
+0.1V
–0.3 V
SRAM
V
CC
s* = 3.0 V
70
70
35
+0.1V
–0.3 V
*: Both V
CC
f and V
CC
s must be in recommended operation range when either part is being accessed.
s
PACKAGE
65-pin plastic FBGA
(BGA-65P-M01)
MB84VD23280FA
-70
(Continued)
FLASH MEMORY
•
0.16
µ
m Process Technology
•
Simultaneous Read/Write operations
(Dual
Bank)
•
FlexBank
TM
*
1
Bank A : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Bank B : 24 Mbit (64 KB
×
48)
Bank C : 24 Mbit (64 KB
×
48)
Bank D : 8 Mbit (8 KB
×
8 and 64 KB
×
15)
Two virtual Banks are chosen from the combination of four physical banks
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
•
Single 3.0 V read, program, and erase
Minimized system level power requirements
• Minimum 100,000 program/erase cycles
•
Sector erase architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word.
Any combination of sectors can be concurrently erased. It also supports full chip erase.
•
HiddenROM region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC input pin
At V
IL
, allows protection of “outermost” 2
×
8 Kbytes on both ends of boot sectors, regardless of sector protection/
unprotection status
At V
IH
, allows removal of boot sector protection
At V
ACC
, increases program performance
•
Embedded Erase
TM
*
2
Algorithms
Automatically preprograms and erases the chip or any sector
•
Embedded Program
TM
*
2
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready/Busy output
(RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic sleep mode
When addresses remain stable, the device automatically switches itself to low power mode.
•
Low V
CC
f write inhibit
≤
2.5 V
•
Program Suspend/Resume
Suspends the program operation to allow a read in another byte
•
Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
•
Please refer to “MBM29DL64DF” data sheet in detailed function
(Continued)
2
MB84VD23280FA
-70
(Continued)
SRAM
•
Power dissipation
Operating: 50 mA Max
Standby: 15
µ
A Max
• Power down features using CE1s and CE2s
• Data retention supply voltage: 1.5 V to 3.1 V
• CE1s and CE2s Chip Select
• Byte data control: LB (DQ
7
to DQ
0
), UB (DQ
15
to DQ
8
)
*1 : FlexBank
TM
is a trademark of Fujitsu Limited, Japan.
*2 : Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
3
MB84VD23280FA
-70
s
PIN ASSIGNMENT
(Top View)
Marking side
A10
N.C.
A9
N.C.
B8
A
11
B7
A
8
B6
WE
B5
WP/ACC
B4
LB
B3
A
7
A2
N.C.
A1
N.C.
B1
N.C.
C9
A
15
C8
A
12
C7
A
19
C6
CE2s
C5
RESET
C4
UB
C3
A
6
C2
A
3
D9
A21
D8
A
13
D7
A
9
D6
A
20
D5
RY/BY
D4
A
18
D3
A
5
D2
A
2
E4
A
17
E3
A
4
E2
A
1
F4
DQ
1
F3
V
SS
F2
A
0
E9
N.C.
E8
A
14
E7
A
10
F9
A
16
F8
SA
F7
DQ
6
G9
CIOf
G8
DQ
15
/A
-1
G7
DQ
13
G6
DQ
4
G5
DQ
3
G4
DQ
9
G3
OE
G2
CEf
H9
Vss
H8
DQ
7
H7
DQ
12
H6
Vccs
H5
Vccf
H4
DQ
10
H3
DQ
0
H2
CE1s
J8
DQ
14
J7
DQ
5
J6
CIOs
J5
DQ
11
J4
DQ
2
J3
DQ
8
K10
N.C.
K9
N.C.
K2
N.C.
K1
N.C.
(BGA-65P-M01)
4
