FUJITSU MICROELECTRONICS
DATA SHEET
DS05-13105-3E
Memory FRAM
CMOS
256 K (32 K
×
8) Bit SPI
MB85RS256
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DESCRIPTION
MB85RS256 is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words
×
8 bits,
using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory
cells.
MB85RS256 adopts the Serial Peripheral Interface (SPI).
The MB85RS256 is able to retain data without using a back-up battery, as is needed for SRAM.
The memory cells used in the MB85RS256 can be used for 10
10
read/write operations, which is a significant
improvement over the number of read and write operations supported by Flash memory and E
2
PROM.
MB85RS256 does not take long time to write data unlike Flash memories nor E
2
PROM, and MB85RS256 takes
no wait time.
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FEATURES
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Bit configuration
Operating power supply voltage
Operating frequency
Serial Peripheral Interface
Operating temperature range
Data retention
High endurance
Package
:
:
:
:
:
:
:
:
32,768 words
×
8 bits
3.0 V to 3.6 V
15 MHz (Max)
SPI (Serial Peripheral Interface)
Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1)
−20 °C
to
+85 °C
10 years (+55
°C)
10 Billion Read/writes
8-pin plastic SOP (FPT-8P-M02)
Copyright©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB85RS256
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PIN ASSIGNMENT
(TOP VIEW)
CS
1
8
V
CC
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
(FPT-8P-M02)
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PIN FUNCTIONAL DESCRIPTIONS
Pin No. Pin Name
Functional description
Chip Select
This is an input pin to make chips select. When CS is “H”, device is in deselect (standby)
status as long as device is not write status internally, and SO becomes High-Z. Other inputs
from pins are ignored for this time. When CS is “L”, device is in select (active) status. CS has
to be “L” before inputting op-code.
Write Protect
This is a pin to control writing to a status register. When WP is “L”, writing to a status register
is not operated.
Hold
This pin is used to interrupt serial input/output without making chips deselect. When HOLD
is “L”, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care.
While the hold operation, CS has to be retained “L”.
Serial Clock
This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising
edge, SO is output synchronously to a falling edge.
Serial Data Input
This is an input pin of serial data. This inputs op-code, address, and writing data.
Serial Data Output
This is an output pin of serial data. Reading data of FRAM memory cell array and status
register data are output. This is High-Z during standby.
Supply Voltage
Ground
1
CS
3
WP
7
HOLD
6
SCK
5
SI
2
8
4
SO
V
CC
GND
2
DS05-13105-3E
MB85RS256
■
BLOCK DIAGRAM
Serial-Parallel Converter
Row-Decoder
SI
FRAM Cell Array
32,768
✕
8
CS
Address Counter
SCK
Control Circuit
FRAM
Status Register
HOLD
Column Decoder/Sense Amp/
Write Amp
WP
Data Register
SO
Parallel-Serial Converter
DS05-13105-3E
3
MB85RS256
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SPI MODE
MB85RS256 corresponds to the SPI mode 0 (CPOL
=
0, CPHA
=
0) , and SPI mode 3 (CPOL
=
1, CPHA
=
1) .
CS
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
SPI Mode 0
CS
SCK
SI
7
MSB
6
5
4
3
2
1
0
LSB
SPI Mode 3
4
DS05-13105-3E
MB85RS256
■
SERIAL PERIPHERAL INTERFACE (SPI)
MB85RS256 works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped
with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use.
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
Microcontroller
MB85RS256
CS
SS1
SS2
HOLD1
HOLD2
HOLD
MB85RS256
CS
HOLD
MOSI : Master Out Slave In
MISO : Master In Slave Out
SS
: Slave Select
System Configuration with SPI Port
Microcontroller
SO
SI
SCK
MB85RS256
CS
HOLD
System Configuration without SPI Port
DS05-13105-3E
5
