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MB90341APFV

Microcontroller, 16-Bit, MROM, F2MC-16LX CPU, 24MHz, CMOS, PQFP100, PLASTIC, LQFP-100

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:FUJITSU(富士通)

厂商官网:http://edevice.fujitsu.com/fmd/en/index.html

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器件参数
参数名称
属性值
是否Rohs认证
不符合
包装说明
LFQFP, QFP100,.7X.9
Reach Compliance Code
compliant
具有ADC
YES
地址总线宽度
24
位大小
16
CPU系列
F2MC-16LX
最大时钟频率
24 MHz
DAC 通道
NO
DMA 通道
YES
外部数据总线宽度
16
JESD-30 代码
S-PQFP-G100
JESD-609代码
e0
长度
14 mm
I/O 线路数量
82
端子数量
100
最高工作温度
105 °C
最低工作温度
-40 °C
PWM 通道
NO
封装主体材料
PLASTIC/EPOXY
封装代码
LFQFP
封装等效代码
QFP100,.7X.9
封装形状
SQUARE
封装形式
FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
认证状态
Not Qualified
RAM(字节)
16384
ROM(单词)
131072
ROM可编程性
MROM
座面最大高度
1.7 mm
速度
24 MHz
最大压摆率
70 mA
最大供电电压
5.5 V
最小供电电压
4.5 V
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
14 mm
uPs/uCs/外围集成电路类型
MICROCONTROLLER
Base Number Matches
1
文档预览
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13730-3E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90340 Series
MB90F342A(S), MB90F342CA(S), MB90F343A(S), MB90F343CA(S), MB90F345A(S), MB90F345CA(S),
MB90F346A(S), MB90F346CA(S), MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S),
MB90341A(S), MB90341CA(S), MB90342A(S), MB90342CA(S), MB90346A(S), MB90346CA(S), MB90347A(S),
MB90347CA(S), MB90348A(S), MB90348CA(S), MB90349A(S), MB90349CA(S), MB90V340A-101/102
s
DESCRIPTION
The MB90340-series with up to 2 FULL-CAN* interfaces and FLASH ROM is especially designed for automotive
and other industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a
normal full CAN approach. With the new 0.35
µm
CMOS technology, Fujitsu now offers on-chip FLASH-ROM
program memory up to 512 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F
2
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
s
PACKAGES
100-pin Plastic QFP
100-pin Plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90340 Series
s
FEATURES
Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided two) is allowed. (devices without S-
suffix only)
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi-
plied PLL clock).
• Built-in Clock Modulation circuit
16 Mbyte CPU memory space
• 24-bit internal addressing
Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes(23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
Increased processing speed
• 4-byte instruction queue
Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 16 external interrupts are supported
Automatic data transfer function independent of CPU
• Expanded intelligent I/O service function (EI
2
OS) : up to 16 channels
• DMA : up to 16 channels
Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (time-base timer mode that is transfered from main clock mode)
• PLL timer mode (time-base timer mode that is transfered from PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
Process
• CMOS technology
I/O port
• General-purpose input/output port (CMOS output)
- 80 ports (devices without S-suffix)
- 82 ports (devices with S-suffix)
(Continued)
2
MB90340 Series
(Continued)
Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit X 16 channels, or 16-bit X 8 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channel (FRT0 : ICU 0/1/2/3, OCU 0/1/2/3, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 8 channels
- 16-bit output compare : (OCU) : 8 channels
Full-CAN interface : up to 2 channels
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
UART (LIN/SCI) : up to 4 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
I
2
C interface* : up to 2 channels (devices with C-suffix only)
• Up to 400 Kbits/s transfer rate
DTP/External interrupt : up to 16 channels, CAN wakeup : up to 2 channels
• Module for activation of expanded intelligent I/O service (EI
2
OS), DMA, and generation of external interrupt.
Delay interrupt generator module
• Generates interrupt request for task switching.
8/10-bit A/D converter : 16/24 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3
µs
(at 24-MHz machine clock, including sampling time)
Program patch function
• Address matching detection for 6 address pointers.
Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
FLASH memory security function
• Protects the content of FLASH memory (FLASH memory device only)
External bus interface
Clock monitor function
* : I
2
C license :
Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these com-
ponents in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined by
Philips.
3
MB90340 Series
s
PRODUCT LINEUP
Part Number
MB90F342A(S), MB90F342CA(S), MB90F343A(S)*
1
, MB90F343CA(S)*
1
,
MB90F345A(S), MB90F345CA(S), MB90F346A(S), MB90F346CA(S),
MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S),
MB90341A(S)*
1
, MB90341CA(S)*
1
, MB90342A(S)*
1
, MB90342CA(S)*
1
,
MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S),
MB90348A(S)*
1
, MB90348CA(S)*
1
, MB90349A(S)*
1
, MB90349CA(S)*
1
MB90V340A-101/102
Parameter
CPU
System clock
F
2
MC-16LX CPU
On-chip PLL clock multiplier (×1,
×2, ×3, ×4, ×6,
1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL
×
6)
MASK ROM, Flash memory
512 Kbytes : MB90F345A(S), MB90F345CA(S)
384 Kbytes : MB90F343A(S), MB90F343CA(S)
256 Kbytes : MB90F342A(S), MB90F342CA(S), MB90F349A(S),
MB90F349CA(S), MB90342A(S), MB90342CA(S),
MB90349A(S), MB90349CA(S)
128 Kbytes : MB90F347A(S), MB90F347CA(S), MB90341A(S),
MB90341CA(S),MB90348A(S), MB90348CA(S), MB90347A(S),
MB90347CA(S)
64 Kbytes : MB90F346A(S), MB90F346CA(S), MB90346A(S),
MB90346CA(S)
20 Kbytes : MB90F343A(S), MB90F343CA(S), MB90F345A(S),
MB90F345CA(S)
16 Kbytes : MB90F342A(S), MB90F342CA(S), MB90F349A(S),
MB90F349CA(S), MB90341A(S), MB90341CA(S),
MB90342A(S), MB90342CA(S), MB90348A(S),
MB90348CA(S), MB90349A(S), MB90349CA(S)
6 Kbytes :
MB90F347A(S), MB90F347CA(S), MB90347A(S),
MB90347CA(S)
2 Kbytes :
MB90F346A(S), MB90F346CA(S), MB90346A(S),
MB90346CA(S)
ROM
External
RAM
30 Kbytes
Emulator-specific
power supply*
2
Technology
Operating
voltage range
Temperature range
Package
0.35
µm
CMOS with regulator for internal
power supply
+
Flash memory with
Charge pump for programming voltage
3.5 V - 5.5 V : at normal operating (not using A/D converter)
4.0 V - 5.5 V : at using A/D converter/Flash programming
4.5 V - 5.5 V : at using external bus
−40 °C
to
+105 °C
QFP-100, LQFP-100
4 channels
Yes
0.35
µm
CMOS with
regulator for internal
power supply
5 V
±
10%
PGA-299
5 channels
UART
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
devices with ‘C’-suffix
: 2ch
devices without ‘C’-suffix :
2 channels
I
2
C (400 Kbps)
(Continued)
4
MB90340 Series
Part Number
MB90F342A(S), MB90F342CA(S), MB90F343A(S)*
1
, MB90F343CA(S)*
1
,
MB90F345A(S), MB90F345CA(S), MB90F346A(S), MB90F346CA(S),
MB90F347A(S), MB90F347CA(S), MB90F349A(S), MB90F349CA(S),
MB90341A(S)*
1
, MB90341CA(S)*
1
, MB90342A(S)*
1
, MB90342CA(S)*
1
,
MB90346A(S), MB90346CA(S), MB90347A(S), MB90347CA(S),
MB90348A(S)*
1
, MB90348CA(S)*
1
, MB90349A(S)*
1
, MB90349CA(S)*
1
MB90V340A-101/102
Parameter
A/D
Converter
16-bit Reload Timer
(4 channels)
16-bit
I/O Timer
(2 channels)
16-bit Output
Compare
(8 channels)
16-bit Input Capture
(8 channels)
devices with ‘C’-suffix
: 24ch
devices without ‘C’-suffix : 16ch
10-bit or 8-bit resolution
Conversion time : Min 3
µs
include sample time (per one channel)
24 input channels
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
=
Machine clock frequency)
Supports External Event Count function
Signals an interrupt when overflowing
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
=
Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
8/16-bit
Sixteen 8-bit reload registers for L pulse width
Programmable Pulse Sixteen 8-bit reload registers for H pulse width
Generator
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
(8 channels)
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
or 128
µs@fosc =
4 MHz
(fsys
=
Machine clock frequency, fosc
=
Oscillation clock frequency)
2 channels :
MB90F342A(S), MB90F342CA(S), MB90F345A(S),
MB90F345CA(S), MB90341A(S), MB90341CA(S),
MB90342A(S), MB90342CA(S)
MB90F346A(S), MB90F346CA(S), MB90F347A(S),
MB90F347CA(S), MB90F349A(S), MB90F349CA(S),
MB90346A(S), MB90346CA(S), MB90347A(S),
MB90347CA(S), MB90348A(S), MB90348CA(S),
MB90349A(S), MB90349CA(S)
1 channel :
3 channels
CAN Interface
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
(Continued)
5
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