FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13710-4E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90580C Series
MB90583C/583CA/F583C/F583CA/587C/587CA/V580B
s
DESCRIPTION
The MB90580C series is a line of general-purpose, Fujitsu 16-bit microcontrollers designed for process control
applications which require high-speed real-time processing, such as consumer products.
While inheriting the AT architecture of the F
2
MC*
1
family, the instruction set for the F
2
MC-16LX CPU core of the
MB90580C series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90580C has an on-chip 32-bit accumulator which
enables processing of long-word data.
The peripheral resources integrated in the MB90580C series include: an 8/10-bit A/D converter, an 8-bit D/A
converter, UARTs (SCI) 0 to 4, an 8/16-bit PPG timer, 16-bit I/O timers (16-bit free-run timer, input capture units
(ICUs) 0 to 3, output compare units (OCUs) 0 and 1), and an IEBus
TM
controller *
2
.
*1: F
2
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
*2: IEBus
TM
is a trademark of NEC Corporation.
s
FEATURES
• Minimum execution time: 62.5 ns/4 MHz oscillation (Uses PLL clock multiplication) maximum multiplier = 4
• Maximum memory space
16 Mbyte
Linear/bank access
(Continued)
s
PACKAGES
100-pin plastic LQFP
100-pin plastic QFP
(FPT-100P-M05)
(FPT-100P-M06)
MB90580C Series
(Continued)
• Instruction set optimized for controller applications
Supported data types: bit, byte, word, and long-word types
Standard addressing modes: 23 types
32-bit accumulator enhancing high-precision operations
Signed multiplication/division and extended RETI instructions
• Enhanced high level language (C) and multitasking support instructions
Use of a system stack pointer
Symmetrical instruction set and barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed: 4 byte instruction queue
• Enhanced interrupt function
Up to eight priority levels programmable
External interrupt inputs: 8 lines
• Automatic data transmission function independent of CPU operation
Up to 16 channels for the extended intelligent I/O service
DTP request inputs: 8 lines
• Internal ROM
FLASH: 128 Kbyte
MASKROM: 128 Kbyte (MB90583C/CA) , 64 Kbyte (MB90587C/CA)
• Internal RAM
FLASH: 6 Kbyte
MASKROM: 6 Kbyte (MB90583C/CA) , 4 Kbyte (MB90587C/CA)
• General-purpose ports
Up to 77 channels (Input pull-up resistor settable for: 22 channels. Output open drain settable for: 8 channels)
• IEBus
TM
controller
*
Three different data transfer rates selectable
Mode 0: 3.9 Kbps (16 bytes/frame)
Mode 1: 17.0 Kbps (32 bytes/frame)
Mode 2: 26.0 Kbps (128 bytes/frame)
*: IEBus
TM
is a trademark of NEC Corporation.
• A/D Converter (RC) : 8 ch
8/10-bit resolution
Conversion time: 34.7
µs
(Min) , 12 MHz operation
• D/A Converter: 2 ch
8-bit resolutions
Setup time: 12.5
µs
• UART : 5 ch
• 8/16 bit PPG : 1 ch
8 bits
×
2 channels: 16 bits
×
1 channel: Mode switching function provided
• 16 bit reload timer: 3 ch
• 16-bit PWC timer: 1 channel
Noise filter provided. Available to pulse width counter
• 16 bit I/O timer
Input capture : 4 ch
Output compare : 2 ch
Free run timer: 1 ch
• Internal clock generator
• Time-base counter/watchdog timer: 18-bit
(Continued)
2
MB90580C Series
(Continued)
• Clock monitor function integrated
• Low-power consumption mode
Sleep mode
Stop mode
Hardware standby mode
CPU intermittent operation mode
• Package: LQFP-100 / QFP-100
• CMOS technology
3
MB90580C Series
s
PRODUCT LINEUP
Part number
Item
Classification
ROM size
RAM size
Clock*
1
Emulator-specific
power supply *
2
MB90587C/CA
MB90583C/CA
MB90F583C/CA
Mass-produced products
(Flash ROM)
128 Kbytes
6 Kbytes
Two clocks /
one clock system
MB90V580B
Development
/
evaluation
product
None
6 Kbytes
Two clocks system
None
Mass-produced products
(MASK ROM)
64 Kbytes
4 Kbytes
128 Kbytes
6 Kbytes
Two clocks /
Two clocks /
one clock system one clock system
CPU functions
The number of instructions: 340
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum execution time: 62.5 ns (at machine clock of 16 MHz)
Interrupt processing time: 1.5
µs
(at machine clock of 16 MHz, minimum value)
General-purpose I/O ports (CMOS output)
General-purpose I/O port (Can be set as open-drain)
General-purpose I/O ports (Input pull-up resistors available)
Total:
: 45
: 8
: 22
: 77
Ports
IEBus
TM
controller
None
Communication mode: Half-duplex, asynchronous communication
Multi-master system
Access control: CDMA/CD
Three modes selectable for different transmission speeds
Transmit buffer: 8-byte FIFO buffer
Receive buffer: 8-byte FIFO buffer
Timebase timer
Watchdog timer
Clock timer
18-bit counter
Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (At oscillation of 4 MHz)
Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(at oscillation of 4 MHz, minimum value)
15-bit counter
Interrupt interval: 1 s, 0.5 s, 0.25 s, 31.25 ms (At oscillation of 32.768 kHz)
Number of channels: 1 (8-bit
×
2 channels)
PPG operation of 8-bit or 16-bit
A pulse wave of given intervals and given duty ratios can be output.
Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz)
Number of channels: 3
Event count provided
Interval: 125 ns to 131 ms (at oscillation of 4 MHz, machine clock of 16 MHz)
Number of channels: 1
Timer function (select the counter timer from three internal clocks.)
Pulse width measuring function (select the counter timer from three internal clocks.)
8/16-bit PPG timer
16-bit reload timer
PWC timer
(Continued)
4
MB90580C Series
(Continued)
Part number
Item
16-bit
free run timer
16-bit
I/O
timer
Output compare
(OCU)
Input capture (ICU)
MB90587C/CA
MB90583C/CA
MB90F583C/CA
MB90V580B
Number of channels: 1
Overflow interrupts
Number of channels: 2
Pin input factor: A match signal of compare register
Number of channels: 4
Rewriting a register value upon a pin input (rising, falling, or both edges)
Number of inputs: 8
DTP/external interrupt circuit Started by a rising edge, a falling edge, an “H” level input, or an “L” level input.
External interrupt circuit or extended intelligent I/O service (EI
2
OS) can be used.
Delayed interrupt generation
module
An interrupt generation module for switching tasks used in real time operating
systems.
Clock synchronized transmission (62.5 Kbps to 1 Mbps)
Clock asynchronized transmission (1202 bps to 9615 bps)
Transmission can be performed by bi-directional serial transmission or by master/
slave connection.
Resolution: 8/10-bit changeable
Number of inputs: 8
One-shot conversion mode (converts selected channel only once)
Scan conversion mode
(converts two or more successive channels and can program up to 8 channels.)
Continuous conversion mode (converts selected channel repeatedly)
Stop conversion mode (converts selected channel and stop operation repeatedly)
8-bit resolution
Number of channels: 2 channels
Based on the R-2R system
Sleep/stop/CPU intermittent operation/clock timer/hardware standby
CMOS
UART0, 1, 2, 3, 4
A/D converter
D/A converter
Low-power consumption
(standby) mode
Process
Power supply voltage for operation
4.5 V to 5.5 V*
3
*1: Connect the oscillator to both terminals XA0 and XA1 for MB90F587C / 583C / F583C.
*2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
*3: Varies with conditions such as the operating frequency (See section “s ELECTRICAL CHARACTERISTICS”).
Assurance for the MB90V580B is given only for operation with a tool at a power supply voltage of 4.5 V to 5.5
V, an operating temperature of 0 to +25
°C,
and an operating frequency of 1 MHz to 16 MHz.
s
PACKAGE AND CORRESPONDING PRODUCTS
Package
FPT-100P-M05
FTP-100P-M06
: Available
×:
Not available
MB90583C/CA
MB90587C/CA
MB90F583C/CA
Note: For more information about each package, see section “s PACKAGE DIMENSIONS”.
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