FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12602-2E
8-bit Proprietary Microcontrollers
CMOS
F
2
MC-8FX MB95110A Series
MB95116A/F118AS/F118AW/FV100B-101
■
DESCRIPTION
The MB95110A series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set,
the microcontrollers contain a variety of peripheral functions.
Note : F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
■
FEATURES
•
F
2
MC-8FX CPU core
Instruction set that is optimum to the controllers
• Multiplication and division instructions
• 16-bit arithmetic operation
• Bit test branch instruction
• Bit manipulation instructions etc.
•
Clock
• Main clock
• Main PLL clock
• Subclock (for dual clock product)
• Sub PLL clock (for dual clock product)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2005-2006 FUJITSU LIMITED All rights reserved
MB95110A Series
(Continued)
•
Timer
• 8/16-bit compound timer
×
2 channels
• 8/16-bit PPG
×
2 channels
• 16-bit PPG
• Timebase timer
• Watch prescaler (for dual clock product)
•
LIN-UART
• Full duplex double buffer
• Clock asynchronous or Clock synchronous serial data transfer capable
•
UART/SIO
• Full duplex double buffer
• Clock asynchronous or Clock synchronous serial data transfer capable
•
I
2
C*
Built-in wake-up function
•
External interrupt
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
•
8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected
•
Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode (for dual clock product)
• Timebase timer mode
•
I/O port:
• The number of maximum ports
•
Single clock product : 39 ports
•
Dual clock product : 37 ports
• Port configuration
•
General-purpose I/O ports (N-ch open drain) : 2 ports
•
General-purpose I/O ports (CMOS)
: Single clock product : 37 ports
Dual clock product : 35 ports
* : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent Rights to use, these com-
ponents in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined by
Philips.
2
MB95110A Series
■
PRODUCT LINEUP
Part number
Parameter
Type
ROM capacity
RAM capacity
Reset output
Option*
1
Clock system
Low voltage
detection reset
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
Selectable
single/dual clock*
2
MB95116A
MASK ROM product
32 Kbytes
1 Kbyte
No
Single clock
No
: 136
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 0.1
µs
(at machine clock frequency 10 MHz)
: 0.9
µs
(at machine clock frequency 10 MHz)
Dual clock
MB95F118AS
MB95F118AW
Flash memory product
60 Kbytes
2 Kbytes
CPU functions
General-purpose I/O
•
Single clock product : 39 ports (N-ch open drain : 2 ports, CMOS : 37 ports)
port
•
Dual clock product : 37 ports (N-ch open drain : 2 ports, CMOS : 35 ports)
Timebase timer
Watchdog timer
Wild register
Peripheral functions
Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz)
Reset generated cycle
At main oscillation clock 10 MHz
: Minimum 105 ms
At sub oscillation clock 32.768 kHz (for dual clock product) : Minimum 250 ms
Capable of replacing 3 bytes of ROM data
Master/slave sending and receiving
Bus error function and arbitration function
Detecting transmitting direction function
Start condition repeated generation and detection functions
Built-in wake-up function
Data transfer capable in UART/SIO
Full duplex double buffer, variable data length (5/6/7/8-bit), built-in baud rate genera-
tor
Transfer rate : 2400 bps to 1250000 bps (at machine clock 10 MHz)
NRZ type transfer format, error detected function
LSB-first or MSB-first can be selected.
Clock synchronous (SIO) or clock asynchronous (UART) serial data transfer capable
Dedicated reload timer allowing a wide range of communication speeds to be set.
Full duplex double buffer.
Capable of serial data transfer synchronous or asynchronous to clock signal.
LIN functions available as the LIN master or LIN slave.
I
2
C
UART/SIO
LIN-UART
8/10-bit A/D convert-
8-bit or 10-bit resolution can be selected.
er(8 channels)
(Continued)
3
MB95110A Series
(Continued)
Part number
Parameter
8/16-bit
compound timer
(2 channels)
MB95116A
MB95F118AS
MB95F118AW
Each channel of the timer can be used as “8-bit timer
×
2 channels” or “16-bit timer
×
1 channel”.
Built-in timer function, PWC function, PWM function, capture function and square
waveform output
Count clock : 7 internal clocks and external clock can be selected.
PWM mode or one-shot mode can be selected.
Counter operating clock : 8 selectable clock sources
Support for external trigger start
Each channel of the PPG can be used as “8-bit PPG
×
2 channels” or “16-bit PPG
×
1 channel”.
Counter operating clock : Eight selectable clock sources
Peripheral functions
16-bit PPG
8/16-bit PPG
(2 channels)
Count clock : Four selectable clock sources (125ms, 250ms, 500ms, or 1s)
Watch counter
Counter value can be set from 0 to 63. (Capable of counting for 1 minute when se-
(for dual clock product)
lecting clock source 1 second and setting counter value to 60)
Watch prescaler
4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s)
(for dual clock product)
External interrupt
(8 channels)
Interrupt by edge detection (rising, falling, or both edges can be selected)
Can be used to recover from standby modes.
Sleep, stop, watch (for dual clock product) , and timebase timer
Standby mode
*1 : For details of option, refer to “■ MASK OPTIONS”.
*2 : Specify clock mode when ordering MASK ROM.
Note : Part number of the evaluation device in MB95110A series is MB95FV100B-101. When using it, the MCU
board (MB2146-301) is required.
4
MB95110A Series
■
SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY)
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value
of main clock oscillation stabilization wait time from among the following four values.
Note that the Evaluation and Flash memory products are fixed their initial value of main clock oscillation stabi-
lization wait time at the maximum value.
Selection of oscillation stabilization wait time
(2
2
−
2) /F
CH
(2
12
−
2) /F
CH
(2
13
−
2) /F
CH
(2
14
−
2) /F
CH
Remarks
0.5
µs
(at main oscillation clock 4 MHz)
Approx. 1.02 ms (at main oscillation clock 4 MHz)
Approx. 2.05 ms (at main oscillation clock 4 MHz)
Approx. 4.10 ms (at main oscillation clock 4 MHz)
■
PACKAGES AND CORRESPONDING PRODUCTS
Part number
Package
LCC-48P-M09
FPT-48P-M26
FPT-52P-M01
BGA-224P-M08
: Available
: Unavailable
* : Under development
*
MB95116A
MB95F118AS
MB95F118AW
MB95FV100B-101
5
模拟电子
