MB96340
SPECIFICATION
FME-MB96340 rev 5
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16FX MB96340 Series
MB96340 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy
migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption
and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 56MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction
cycle time of 17.8ns going together with excellent EMI behavior. An on-chip clock modulation circuit significantly
reduces emission peaks in the frequency spectrum. The emitted power is minimised by the on-chip voltage
regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies
for peripheral resources independent of the CPU speed.
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DESCRIPTION
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MB96340 Series
Specification
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FEATURES
Feature
Technology
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 56 MHz internal, 17.8 ns instruction cycle time
CPU
Description
MB96340
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
• Signed multiply (16-bit
×
16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1..25, x1 when PLL stop)
• 32-100 kHz subsystem quartz clock
• 3-16 MHz external quartz clock, up to 4MHz external clock
• 100kHz/2MHz internal RC clock for quick and save startup, oscillator stop detection,
watchdog
• Clock source selectable from main- and subclock oscillator (partnumber suffix “W”)
on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
System clock
On-chip voltage regula- • Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
tor
and low power consumption figures
Low voltage reset
Code Security
Memory Patch Function
DMA
Interrupts
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
Timers
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• Watchdog Timer
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
• Two independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
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• 8-byte instruction execution queue
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MB96340 Series
Feature
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
Description
• Supports CAN protocol version 2.0 part A and B
Specification
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
USART
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
• Up to 400 kbit/s
• SAR-type
I2C
• Master and Slave functionality, 8-bit and 10-bit addressing
• 10bit resolution
A/D converter
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
A/D Converter Refer-
ence Voltage switch
Reload Timers
• 2 independant positive A/D converter reference voltages available
• 16-bit wide
Free Running Timers
Input Capture Units
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
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• Event count function
• 16-bit wide
• 16-bit wide
• Prescaler with 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
of peripheral clock frequency
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
, 1/2
7
,1/2
8
of
peripheral clock frequency
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
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Specification
Feature
Description
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
Programmable Pulse
Generator
• PWM operation and one-shot operation
MB96340
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer overflow as clock input
• Can be triggered by software or reload timer
• Can be clocked either from sub oscillator (devices with partnumber suffix “W”),main
oscillator or from the RC oscillator
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
• Read/write accessible second/minute/hour registers
• Can signal interrupts every halfsecond/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32
kHz clock input (devices with partnumber suffix “W”) clock input
• Edge sensitive or level sensitive
• Interrupt mask and pending bit per channel
External Interrupts
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
• 8-bit or 16-bit bidirectional data
• Pin shared with external interrupt 0.
• Up to 24-bit addresses
• 6 chip select signals
• Wait state request
Non Maskable Interrupt
External bus interface
Alarm comparators
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• Timing programmable
• Multiplexed address/data lines
• External bus master possible
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
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Real Time Clock
Y
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电源技术
