MB96690 Series
F
2
MC-16FX , 16-bit Proprietary
Microcontroller
MB96690 series is based on Cypress advanced F
2
MC-16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established F
2
MC-16LX family thus allowing for easy
migration of F
2
MC-16LX Software to the new F
2
MC-16FX products. F
2
MC-16FX product improvements compared to
the previous generation include significantly improved performance - even at the same operation frequency, reduced
power consumption and faster start-up time.
For high processing speed at optimized power consumption an internal PLL can be selected to supply the
CPU with up to 32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum
instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the
on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable
operation frequencies for peripheral resources independent of the CPU speed.
Features
Technology
0.18µm CMOS
On-chip voltage regulator
Internal voltage regulator supports a wide MCU
supply voltage range (Min=2.7V), offering low power
consumption
CPU
F
2
MC-16FX CPU
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different
addressing modes, barrel shift, variety of pointers)
8-byte instruction queue
Signed multiply (16-bit
×
16-bit) and divide
(32-bit/16-bit) instructions available
Low voltage detection function
Reset is generated when supply voltage falls below
programmable reference voltage
Code Security
Protects Flash Memory content from unintended
read-out
System clock
On-chip PLL clock multiplier (×1 to
×8, ×1
when PLL
stop)
4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator
depends on Q-factor)
Up to 8MHz external clock for devices with fast clock
input feature
32.768kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe
startup, clock stop detection function, watchdog
Clock source selectable from mainclock oscillator,
subclock oscillator and on-chip RC oscillator,
independently for CPU and 2 clock domains of
peripherals
The subclock oscillator is enabled by the Boot ROM
program controlled by a configuration marker after a
Power or External reset
Low Power Consumption - 13 operating modes
(different Run, Sleep, Timer, Stop modes)
DMA
Automatic transfer function independent of CPU, can
be assigned freely to resources
Interrupts
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1Mbps
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of
message objects)
Maskable interrupt
Cypress Semiconductor Corporation
Document Number: 002-04717 Rev *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 19, 2016
MB96690 Series
Disabled Automatic Retransmission mode for Time
Triggered CAN applications
Programmable loop-back mode for self-test operation
Free-Running Timers
Signals an interrupt on overflow, supports timer clear
upon match with Output Compare (0, 4)
1
2
3
4
5
6
7
Prescaler with 1, 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 , 1/2 ,
8
1/2 of peripheral clock frequency
USART
Full duplex USARTs (SCI/LIN)
Wide range of baud rate settings using a dedicated
reload timer
Special synchronous options for adapting to different
synchronous serial protocols
LIN functionality working either as master or slave
LIN device.
Extended support for LIN-Protocol (with 16-byte FIFO
for selected channels) to reduce interrupt load.
Input Capture Units
16-bit wide
Signals an interrupt upon external event
Rising edge, Falling edge or Both (rising & falling)
edges sensitive
Output Compare Units
16-bit wide
Signals an interrupt when a match with Free-running
Timer occurs
A pair of compare registers can be used to generate
an output signal
I
2
C
Up to 400kbps
Master and Slave functionality, 7-bit and 10-bit
addressing
Programmable Pulse Generator
16-bit down counter, cycle and duty setting registers
Can be used as 2 ×8-bit PPG
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of
peripheral clock as counter clock or of selected
Reload timer underflow as clock input
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
Start delay
A/D converter
SAR-type
8/10-bit resolution
Signals interrupt on conversion end, single
conversion mode, continuous conversion mode, stop
conversion mode, activation by software, external
trigger, reload timers and PPGs
Range Comparator Function
Scan disable Function
ADC Pulse Detection Function
Source Clock Timers
Three independent clock timers (23-bit RC clock
timer, 23-bit Main clock timer, 17-bit Sub clock timer)
Stepping Motor Controller
Stepping Motor Controller with integrated high
current output drivers
Four high current outputs for each channel
Two synchronized 8/10-bit PWMs per channel
Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6,
1/8, 1/10, 1/12, 1/16 of peripheral clock
Dedicated power supply for high current output
drivers
Hardware Watchdog Timer
Hardware watchdog timer is active after reset
Window function of Watchdog Timer is used to select
the lower window limit of the watchdog interval
Reload Timers
16-bit wide
Prescaler with 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
of
peripheral clock frequency
Event count function
Document Number: 002-04717 Rev *A
Page 2 of 75
MB96690 Series
LCD Controller
LCD controller with up to 4COM ×36SEG
Internal or external voltage generation
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
Fixed 1/3 bias
Programmable frame period
Clock source selectable from four options (main clock,
peripheral clock, subclock or RC oscillator clock)
Internal divider resistors or external divider resistors
On-chip data memory for display
LCD display can be operated in Timer Mode
Blank display: selectable
All SEG, COM and V pins can be switched between
general and specialized purposes
Non Maskable Interrupt
Disabled after reset, can be enabled by Boot-ROM
depending on ROM configuration block
Once enabled, cannot be disabled other than by
reset
High or Low level sensitive
Pin shared with external interrupt 0
I/O Ports
Most of the external pins can be used as general
purpose I/O
All push-pull outputs(except when used as I
2
C
SDA/SCL line)
Bit-wise programmable as input/output or peripheral
signal
Bit-wise programmable input enable
One input level per GPIO-pin (either Automotive or
CMOS hysteresis)
Bit-wise programmable pull-up resistor
Sound Generator
8-bit PWM signal is mixed with tone frequency from
16-bit reload counter
PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of
peripheral clock
Built-in On Chip Debugger (OCD)
One-wire debug tool interface
Break function:
Hardware break: 6 points (shared with code
event)
Software break: 4096 points
Event function
Code event: 6 points (shared with hardware
break)
Data event: 6 points
Event sequencer: 2 levels + reset
Execution time measurement function
Trace function: 42 branches
Security function
Real Time Clock
Operational on main oscillation (4MHz), sub
oscillation (32kHz) or RC oscillation (100kHz/2MHz)
Capable to correct oscillation deviation of Sub clock
or RC oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half
second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s
clock
External Interrupts
Edge or Level sensitive
Interrupt mask bit per channel
Each available CAN channel RX has an external
interrupt for wake-up
Selected USART channels SIN have an external
interrupt for wake-up
Document Number: 002-04717 Rev *A
Page 3 of 75
MB96690 Series
Flash Memory
Dual operation flash allowing reading of one Flash
bank while programming or erasing the other bank
Command sequencer for automatic execution of
programming algorithm and for supporting DMA for
programming of the Flash Memory
Supports automatic programming, Embedded
Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the automatic
algorithm
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the
Flash
Low voltage detection during Flash erase or write
Cypress provides information facilitating product development via the following website.
The website contains information useful for customers.
http://www.cypress.com/cypress-microcontrollers
Document Number: 002-04717 Rev *A
Page 4 of 75
MB96690 Series
Contents
1.
Product Lineup ...................................................................................................................................................... 7
2.
Block Diagram ....................................................................................................................................................... 8
3.
Pin Assignment ..................................................................................................................................................... 9
4.
Pin Description .................................................................................................................................................... 10
5.
Pin Circuit Type ................................................................................................................................................... 12
6.
I/O Circuit Type.................................................................................................................................................... 15
7.
Memory Map ........................................................................................................................................................ 22
8.
RAM start Addresses .......................................................................................................................................... 23
9.
User ROM Memory Map For Flash Devices ...................................................................................................... 24
10. Serial Programming Communication Interface ................................................................................................ 25
11. Interrupt Vector Table ......................................................................................................................................... 26
12. Handling Precautions ......................................................................................................................................... 30
12.1 Precautions for Product Design .......................................................................................................................... 30
12.2 Precautions for Package Mounting..................................................................................................................... 31
12.3 Precautions for Use Environment ....................................................................................................................... 33
13. Handling Devices ................................................................................................................................................ 34
13.1 Latch-up prevention............................................................................................................................................ 34
13.2 Unused pins handling ......................................................................................................................................... 34
13.3 External clock usage .......................................................................................................................................... 34
13.3.1 Single phase external clock for Main oscillator ................................................................................................... 34
13.3.2 Single phase external clock for Sub oscillator ..................................................................................................... 35
13.3.3 Opposite phase external clock ............................................................................................................................ 35
13.4 Notes on PLL clock mode operation................................................................................................................... 35
13.5 Power supply pins (Vcc/Vss) .............................................................................................................................. 35
13.6 Crystal oscillator and ceramic resonator circuit .................................................................................................. 35
13.7 Turn on sequence of power supply to
A/D
converter and analog inputs ............................................................ 36
13.8 Pin handling when not using the A/D converter .................................................................................................. 36
13.9 Notes on Power-on............................................................................................................................................. 36
13.10 Stabilization of power supply voltage ................................................................................................................. 36
13.11 SMC power supply pins ...................................................................................................................................... 36
13.12 Serial communication ......................................................................................................................................... 36
13.13 Mode Pin (MD) ................................................................................................................................................... 36
14. Electrical Characteristics ................................................................................................................................... 37
14.1 Absolute Maximum Ratings ................................................................................................................................ 37
14.2 Recommended Operating Conditions ................................................................................................................ 39
14.3 DC Characteristics ............................................................................................................................................. 40
14.3.1 Current Rating..................................................................................................................................................... 40
14.3.2 Pin Characteristics .............................................................................................................................................. 43
14.4 AC Characteristics.............................................................................................................................................. 47
14.4.1 Main Clock Input Characteristics......................................................................................................................... 47
14.4.2 Sub Clock Input Characteristics .......................................................................................................................... 48
14.4.3 Built-in RC Oscillation Characteristics ................................................................................................................. 49
14.4.4 Internal Clock Timing .......................................................................................................................................... 49
14.4.5 Operating Conditions of PLL ............................................................................................................................... 50
14.4.6 Reset Input.......................................................................................................................................................... 50
14.4.7 Power-on Reset Timing ...................................................................................................................................... 51
Document Number: 002-04717 Rev *A
Page 5 of 75
