MB9A140NB Series
32-Bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9A140NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
2
such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I C).
The products which are described in this datasheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM Cortex -M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC):
1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
®
®
External Bus Interface
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
[1]
Supports SRAM, NOR Flash memory device
24-bit System timer (Sys Tick): System timer for OS task
management
Maximum area size: Up to 256 MB
Supports Address/Data multiplex
Supports external RDY function
[1]: MB9AF141LB, F142LB and F144LB do not support
External Bus Interface.
On-chip Memories
[Flash memory]
Dual operation Flash memory
Operation Flash memory has the upper bank and the
lower bank.
So, this series could implement erase, write and read
operations
for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
Dual
Multi-function Serial Interface (Max 8 channels)
4 channels with 16 steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
I2C
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control
[1]
: Automatically control the
transmission by CTS/RTS (only ch.4)
SRAM0: Up to 16 KB
SRAM1: Up to 16 KB
Various error detection functions available (parity errors,
framing errors, and overrun errors)
[1]: MB9AF141LB, F142LB and F144LB do not support
Hardware Flow control.
Cypress Semiconductor Corporation
Document Number: 002-05637 Rev.*A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 7, 2016
MB9A140NB Series
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
2
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast general-purpose I/O Ports@100 pin Package
Some ports are 5 V tolerant I/O.
See Pin Description to confirm the corresponding pins.
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Transfer address area: 32-bit (4 GB)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Free-running
Periodic (=Reload)
One-shot
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
HDMI-CEC transmitter
Header
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion:
4 steps)
block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
HDMI-CEC receiver
Automatic
ACK reply function available
Line error detection function available
Remote control receiver
4
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
bytes reception buffer
Repeat code detection function available
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Document Number: 002-05637 Rev.*A
Page 2 of 114
MB9A140NB Series
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
01 to 99.
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute/Second/A day of the week.) is
available. This function is also available by specifying only
Year, Month, Day, Hour or Minute.
Main Clock
Sub Clock
Built-in high-speed CR Clock
Built-in low-speed CR Clock
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
: 4 MHz to 48 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer
mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
The Hardware watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption modes except RTC, Stop,
Deep Standby RTC and Deep Standby Stop modes.
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
External clock failure (clock stop) is detected, reset is
asserted.
External frequency anomaly is detected, interrupt or reset is
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Document Number: 002-05637 Rev.*A
Page 3 of 114
MB9A140NB Series
Low-Power Consumption Mode
Six low-power consumption modes supported.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM).
[1]
[1]: MB9AF141LB/MB, F142LB/MB and F144LB/MB support
only SWJ-DP.
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Unique ID
Unique value of the device (41-bit) is set.
Deep Standby Stop (selectable between keeping the value of
RAM and not)
Power Supply
Wide range voltage: VCC = 1.65 V to 3.6 V
Document Number: 002-05637 Rev.*A
Page 4 of 114
MB9A140NB Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 16
5. I/O Circuit Type................................................................................................................................................................ 39
6. Handling Precaution ....................................................................................................................................................... 44
6.1
Precautions for Product Design ................................................................................................................................... 44
6.2
Precautions for Package Mounting .............................................................................................................................. 45
6.3
Precautions for Use Environment ................................................................................................................................ 46
7. Handling Devices ............................................................................................................................................................ 47
8. Block Diagram ................................................................................................................................................................. 49
9. Memory Size .................................................................................................................................................................... 50
10. Memory Map .................................................................................................................................................................... 50
11. Pin Status in Each CPU State ........................................................................................................................................ 53
12. Electrical Characteristics ............................................................................................................................................... 60
12.1 Absolute Maximum Ratings ......................................................................................................................................... 60
12.2 Recommended Operating Conditions.......................................................................................................................... 61
12.3 DC Characteristics....................................................................................................................................................... 62
12.3.1 Current Rating .............................................................................................................................................................. 62
12.3.2 Pin Characteristics ....................................................................................................................................................... 65
12.4 AC Characteristics ....................................................................................................................................................... 66
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 66
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 67
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 67
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) .................................................. 68
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main PLL)
68
12.4.6 Reset Input Characteristics .......................................................................................................................................... 69
12.4.7 Power-on Reset Timing................................................................................................................................................ 69
12.4.8 External Bus Timing ..................................................................................................................................................... 70
12.4.9 Base Timer Input Timing .............................................................................................................................................. 77
12.4.10 CSIO/UART Timing .................................................................................................................................................. 78
12.4.11 External Input Timing ................................................................................................................................................ 86
2
12.4.12 I C Timing ................................................................................................................................................................. 87
12.4.13 ETM Timing .............................................................................................................................................................. 88
12.4.14 JTAG Timing ............................................................................................................................................................. 89
12.5 12-bit A/D Converter .................................................................................................................................................... 90
12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 93
12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 93
12.6.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 94
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 95
12.7.1 Write / Erase time......................................................................................................................................................... 95
12.7.2 Erase/write cycles and data hold time .......................................................................................................................... 95
12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 96
12.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 96
12.8.2 Return Factor: Reset .................................................................................................................................................... 98
Document Number: 002-05637 Rev.*A
Page 5 of 114
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