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About Cypress
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automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
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MB9A340NB Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9A340NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the ARM
®
Cortex
®
-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I
2
C).
The products which are described in this data sheet are placed into TYPE6 product categories in FM3 Family Peripheral Manual.
Features
32-bit ARM
®
Cortex
®
-M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
External Bus Interface*
Supports SRAM, NOR Flash memory device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
*: MB9AF341LB, F342LB and F344LB do not support
External Bus Interface.
24-bit System timer (Sys Tick): System timer for OS task
management
On-chip Memories
[Flash memory]
Dual operation Flash memory
Dual
Operation Flash memory has the upper bank and the
lower bank.
So, this series could implement erase, write and read
operations
for each bank simultaneously.
Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank
+ 16 Kbytes lower bank)
Work area: 32 Kbytes (lower bank)
USB Interface
The USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
[USB device]
USB2.0 Full-Speed supported
Max 6 EndPoint supported
EndPoint
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
0 is control transfer
EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or
Isochronous-transfer
EndPoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 is comprised of Double Buffers.
The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5: 64 bytes
- Endpoint 1: 256 bytes
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
[USB host]
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
Automatic detection of connected/disconnected USB Device
Automatic processing of the IN/OUT token handshake
packet
Max 256-byte packet-length supported
Wake-up function supported
•
198 Champion Court
•
San Jose, CA 95134-1709
•
Cypress Semiconductor Corporation
Document Number: 002-05635 Rev.*B
408-943-2600
Revised July 26, 2017
MB9A340NB Series
Multi-function Serial Interface (Max 8 channels)
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 2.0 μs @ 2.7 V to 3.6 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
I
2
C
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control* : Automatically control the
transmission by CTS/RTS (only ch.4)
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General-Purpose I/O Port
Various error detection functions available (parity errors,
framing errors, and overrun errors)
*: MB9AF341LB, F342LB and F344LB do not support
Hardware Flow control.
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[I
2
C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast general-purpose I/O Ports@100 pin Package
Some ports are 5V tolerant I/O.
See Pin Description to confirm the corresponding pins.
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Free-running
Periodic (=Reload)
One-shot
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Document Number: 002-05635 Rev.*B
Page 2 of 126
MB9A340NB Series
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
HDMI-CEC transmitter
block automatic transmission by judging Signal
free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output
CEC transmission by setting 1 byte data
Generating transmission status interrupt when transmitting
1 block (1 byte data and EOM/ACK)
Header
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
HDMI-CEC receiver
Automatic
ACK reply function available
Line error detection function available
Remote control receiver
4
bytes reception buffer
Repeat code detection function available
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
Built-in high-speed CR Clock: 4 MHz
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Built-in low-speed CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Watch Counter
The Watch counter is used for wake up from sleep and timer
mode.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
The Hardware watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption modes except RTC, Stop,
Deep Standby RTC, Deep Standby Stop modes.
External clock failure (clock stop) is detected, reset is
asserted.
External frequency anomaly is detected, interrupt or reset is
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-05635 Rev.*B
Page 3 of 126
MB9A340NB Series
Low-Power Consumption Mode
Six low-power consumption modes supported.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM).*
*: MB9AF341LB/MB, F342LB/MB and F344LB/MB support
only SWJ-DP.
Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of
RAM and not)
Unique ID
Unique value of the device (41-bit) is set.
Deep Standby Stop (selectable between keeping the value of
RAM and not)
Power Supply
Wide range voltage: VCC = 1.65 V to 3.6 V
VCC = 3.0 V to 3.6 V (when USB is used)
Document Number: 002-05635 Rev.*B
Page 4 of 126
stm32/stm8
