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FUJITSU SEMICONDUCTOR

DATA SHEET

DS709-00001-0v01-E

32-bit ARM

Cortex

-M4F based Microcontroller

MB9B560R Series

MB9BF566M/N/R, MB9BF567M/N/R,

MB9BF568M/N/R



DESCRIPTION

The MB9B560R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers

with high-performance and competitive cost.

These series are based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM, and has

peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN,

UART, CSIO, I

C, LIN).

The products which are described in this data sheet are placed into TYPE4 product categories in "FM4

Family PERIPHERAL MANUAL".

Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.

2013.6

MB9B560R Series



FEATURES



32-bit ARM Cortex-M4F Core

・

Processor version: r2p1

・

Up to 160 MHz Frequency Operation

・

FPU built-in

・

Support DSP instruction

・

Memory Protection Unit (MPU): improves the reliability of an embedded system

・

Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128

peripheral interrupts and 16 priority levels

・

24-bit System timer (Sys Tick): System timer for OS task management



On-chip Memories

[Flash memory]

These series are based on two independent on-chip Flash memories.

・

MainFlash memory

・

Up to 1024 Kbytes

・

Built-in Flash Accelerator System with 16 Kbytes trace buffer memory

・

The read access to Flash memory can be achieved without wait-cycle up to operation frequency of

72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory

can be obtained by Flash Accelerator System.

・

Security function for code protection

・

WorkFlash memory

・

32 Kbytes

・

Read cycle:

・6wait-cycle:

the operation frequency more than 120 MHz, and up to 160 MHz

・4wait-cycle:

the operation frequency more than 72 MHz, and up to 120 MHz

・2wait-cycle:

the operation frequency more than 40 MHz, and up to 72 MHz

・0wait-cycle:

the operation frequency up to 40MHz

・

Security function is shared with code protection

[SRAM]

This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to

I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of

Cortex-M4F core.

・

SRAM0: Up to 64 Kbytes

・

SRAM1: Up to 32 Kbytes

・

SRAM2: Up to 32 Kbytes



External Bus Interface

・

Supports SRAM, NOR, NAND Flash and SDRAM device

・

Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)

・

8/16-bit Data width

・

Up to 25-bit Address bit

・

Supports Address/Data multiplex

・

Supports external RDY function

・

Supports scramble function

・

Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to

0xDFFF_FFFF in 4 Mbytes units.

・

Possible to set two kinds of the scramble key

Note: It is necessary to prepare the dedicated software library to use the scramble function.

DS709-00001-0v01-E

MB9B560R Series



USB Interface

USB interface is composed of Function and Host.

[USB function]

・

USB2.0 Full-Speed supported

・

Max 6 EndPoint supported

・

EndPoint 0 is control transfer

・

EndPoint 1, 2 can be selected Bulk-transfer, Interrupt-transfer or Isochronous-transfer

・

EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer

・

EndPoint 1 to 5 comprise Double Buffer

[USB host]

・

USB2.0 Full/Low-speed supported

・

Bulk-transfer, interrupt-transfer and Isochronous-transfer support

・

USB Device connected/dis-connected automatically detect

・

IN/OUT token handshake packet automatically

・

Max 256-byte packet-length supported

・

Wake-up function supported



CAN Interface (Max 2 channels)

・

Compatible with CAN Specification 2.0A/B

・

Maximum transfer rate: 1 Mbps

・

Built-in 32 message buffer



Multi-function Serial Interface (Max 8 channels)

・

64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication

mode or bit length.)

・

Operation mode is selectable from the followings for each channel.

・

UART

・

CSIO

・

LIN

・

[UART]

・

Full-duplex double buffer

・

Selection with or without parity supported

・

Built-in dedicated baud rate generator

・

External clock available as a serial clock

・

Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)

・

Various error detect functions available (parity errors, framing errors, and overrun errors)

[CSIO]

・

Full-duplex double buffer

・

Built-in dedicated baud rate generator

・

Overrun error detect function available

・

Serial chip select function (ch.6 and ch.7 only)

・

Supports high-speed SPI (ch.4 and ch.6 only)

・

Data length 5 to 16-bit

[LIN]

・

LIN protocol Rev.2.1 supported

・

Full-duplex double buffer

・

Master/Slave mode supported

・

LIN break field generation (can change to 13 to 16-bit length)

・

LIN break delimiter generation (can change to 1 to 4-bit length)

・

Various error detect functions available (parity errors, framing errors, and overrun errors)

・

Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported

・

Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3 and ch.7) supported

DS709-00001-0v01-E

MB9B560R Series



DMA Controller (8 channels)

DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.

・

8 independently configured and operated channels

・

Transfer can be started by software or request from the built-in peripherals

・

Transfer address area: 32-bit (4 Gbytes)

・

Transfer mode: Block transfer/Burst transfer/Demand transfer

・

Transfer data type: bytes/half-word/word

・

Transfer block count: 1 to 16

・

Number of transfers: 1 to 65536



DSTC (Descriptor System data Transfer Controller) (128 channels)

The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor

system and, following the specified contents of the Descriptor which has already been constructed on the

memory, can access directly the memory /peripheral device and performs the data transfer operation.

It supports the software activation, the hardware activation and the chain activation functions.



A/D Converter (Max 24 channels)

[12-bit A/D Converter]

・

Successive Approximation type

・

Built-in 3 units

・

Conversion time: 0.5μs @ 5V

・

Priority conversion available (priority at 2levels)

・

Scanning conversion mode

・

Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:

4steps)



DA converter (Max 2 channels)

・

R-2R type

・

12-bit resolution



Base Timer (Max 8 channels)

Operation mode is selectable from the followings for each channel.

・

16-bit PWM timer

・

16-bit PPG timer

・

16/32-bit reload timer

・

16/32-bit PWC timer



General Purpose I/O Port

This series can use its pins as general purpose I/O ports when they are not used for external bus or

peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function

can be allocated.

・

Capable of pull-up control per pin

・

Capable of reading pin level directly

・

Built-in the port relocate function

・

Up to 100 high-speed general-purpose I/O ports @ 120pin Package

・

Some pin is 5V tolerant I/O.

See "PIN DESCRIPTION" and "I/O CIRCUIT TYPE" for the corresponding pins.

DS709-00001-0v01-E

MB9B560R Series



Multi-function Timer (Max 2 units)

The Multi-function timer is composed of the following blocks.

Minimum resolution : 6.25 ns

・

16-bit free-run timer × 3ch./unit

・

Input capture × 4ch./unit

・

Output compare × 6ch./unit

・

A/D activation compare × 6ch./unit

・

Waveform generator × 3ch./unit

・

16-bit PPG timer × 3ch./unit

The following function can be used to achieve the motor control.

・

PWM signal output function

・

DC chopper waveform output function

・

Dead time function

・

Input capture function

・

A/D convertor activate function

・

DTIF (Motor emergency stop) interrupt function



Real-time clock (RTC)

The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.

・

Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the

week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.

・

Timer interrupt function after set time or each set time.

・

Capable of rewriting the time with continuing the time count.

・

Leap year automatic count is available.



Quadrature Position/Revolution Counter (QPRC) (Max 2 channels)

The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position

encoder. Moreover, it is possible to use up/down counter.

・

The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.

・

16-bit position counter

・

16-bit revolution counter

・

Two 16-bit compare registers



Dual Timer (32/16-bit Down Counter)

The Dual Timer consists of two programmable 32/16-bit down counters.

Operation mode is selectable from the followings for each channel.

・

Free-running

・

Periodic (=Reload)

・

One-shot



Watch Counter

The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the

main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source.

Interval timer: up to 64s (Max) @ Sub Clock : 32.768 kHz

DS709-00001-0v01-E

型号	MB9BF566RPMC	MB9BF566MPMC1	MB9BF566NBGL	MB9BF566NPQC	MB9BF566RBGL
描述	RISC Microcontroller, CMOS	RISC Microcontroller, CMOS	RISC Microcontroller, CMOS	RISC Microcontroller, CMOS	RISC Microcontroller, CMOS
厂商名称	FUJITSU(富士通)	FUJITSU(富士通)	FUJITSU(富士通)	FUJITSU(富士通)	FUJITSU(富士通)
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow
技术	CMOS	CMOS	CMOS	CMOS	CMOS
uPs/uCs/外围集成电路类型	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC	MICROCONTROLLER, RISC