SPANSION Flash Memory
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20842-4E
FLASH MEMORY
CMOS
4M (512K
×
8) BIT
MBM29F040C
-55/-70/-90
s
FEATURES
•
•
•
Single 5.0 V read, program and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
Compatible with JEDEC-standard byte-wide pinouts
32-pin PLCC (Package suffix: PD)
32-pin TSOP(I) (Package suffix: PF)
32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program™ Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Low V
CC
write inhibit
≤
3.2 V
Sector protection
Hardware method disables any combination of sectors from write or erase operations
Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
•
•
•
•
•
•
•
•
•
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
MBM29F040C
-55/-70/-90
s
PACKAGE
32-pin Plastic QFJ (PLCC)
Marking Side
(LCC-32P-M02)
32-pin Plastic TSOP (I)
Marking Side
32-pin Plastic TSOP (I)
Marking Side
(FPT-32P-M24 — Assembly: Malaysia)
(FPT-32P-M25 — Assembly: Malaysia)
2
MBM29F040C
-55/-70/-90
s
GENERAL DESCRIPTION
The MBM29F040C is a 4M-bit, 5.0 V-only Flash memory organized as 512K bytes of 8 bits each. The
MBM29F040C is offered in a 32-pin PLCC and 32-pin TSOP(I) package. This device is designed to be
programmed in-system with the standard system 5.0 V V
CC
supply. A 12.0 V V
PP
is not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F040C offers access times 55 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F040C is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 12.0 V Flash or EPROM devices.
The MBM29F040C is programmed by executing the program command sequence. This will invoke the Embedded
Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds. Erase is
accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which
is an internal algorithm that automatically preprograms the array if it is not already programmed before executing
the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell
margin.
Any individual sector is typically erased and verified in 1 second. (If already completely preprogrammed.)
The device also features a sector erase architecture. The sector mode allows for 64K byte sectors of memory
to be erased and reprogrammed without affecting other sectors. The MBM29F040C is erased when shipped
from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
or by the Toggle Bit feature on DQ
6
. Once the end of a program or erase cycle has been completed, the device
internally resets to the read mode.
Fujitsu's Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability and cost effectiveness. The MBM29F040C memory electrically erases the entire chip or all
bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot electron injection.
3
MBM29F040C
-55/-70/-90
s
FLEXIBLE SECTOR-ERASE ARCHITECTURE
• 64K Byte per sector
• Individual-sector, multiple-sector, or bulk-erase
capability
• Individual or multiple-sector protection is user
definable
7FFFFH
6FFFFH
5FFFFH
64K byte per sector
4FFFFH
3FFFFH
2FFFFH
1FFFFH
0FFFFH
00000H
4
