FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20879-2E
FLASH MEMORY
CMOS
16M (2M
×
8/1M
×
16) BIT
MBM29F160TE/BE
-55/-70/-90
s
GENERAL DESCRIPTION
The MBM29F160TE/BE is a 16M-bit, 5.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words
of 16 bits each. The MBM29F160TE/BE is offered in a 48-pin TSOP (I) package. The device is designed to be
programmed in-system with the standard system 5.0 V V
CC
supply. 12.0 V V
PP
is not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29F160TE/BE offers access times of 55 ns, 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F160TE/BE is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input
to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 12.0 V Flash or EPROM devices.
(Continued)
s
PRODUCT LINE UP
Part No.
Ordering Part No.
V
CC
= 5.0 V±5%
V
CC
= 5.0 V±10%
-55
—
55
55
30
MBM29F160TE/160BE
—
-70
70
70
30
—
-90
90
90
40
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s
PACKAGES
48-pin plastic TSOP (I)
Marking Side
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
(Continued)
The MBM29F160TE/BE is programmed by executing the program command sequence. This will invoke the
Embedded Program
TM
* Algorithm which is an internal algorithm that automatically times the program pulse
widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5
seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded
Erase
TM
* Algorithm which is an internal algorithm that automatically preprograms the array if it is not already
programmed before executing the erase operation. During erase, the device automatically times the erase pulse
widths and verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F160TE/BE is erased when shipped from the factory.
The device features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29F160TE/BE also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29F160TE/BE memory electrically erases all bits
within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word
at a time using the EPROM programming mechanism of hot electron injection.
* :
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
2
MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
s
FEATURES
• 0.23
µm
Process Technology
• Single 5.0 V read, program and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP (I) (Package suffix: TN-Normal Bend Type, TR-Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
55 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program Algorithms
Automatically programs and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Low V
CC
write inhibit
≤
4.2 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same devic
• Hardware RESET pin
Resets internal state machine to the read mode
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
• In accordance with CFI (Common Flash Memory Interface)
• WP Input pin (Hardware Protect)
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
At V
IH
, allows removal of boot sector protection
At open, allows removal of boot sector protection (MBM29F160TE/BE)
3
MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
s
PIN ASSIGNMENT
TSOP(I)
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
19
N.C.
WE
RESET
N.C.
N.C.
RY/BY
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
(Marking Side)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
16
BYTE
V
SS
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
DQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
V
SS
CE
A
0
Standard Pinout
(FPT-48P-M19)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
RY/BY
N.C.
N.C.
RESET
WE
N.C.
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
Reverse Pinout
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
45
45
46
47
48
A
0
CE
V
SS
OE
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
13
DQ
6
DQ
14
DQ
7
DQ
15
/A
-1
V
SS
BYTE
A
16
(FPT-48P-M20)
4
MBM29F160TE
-55/-70/-90
/MBM29F160BE
-55/-70/-90
s
BLOCK DIAGRAM
DQ
0
to DQ
15
V
CC
V
SS
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
Input/Output
Buffer
WE
BYTE
RESET
WP
Command
Register
Program Voltage
Generator
CE
OE
Chip Enable
Output Enable
Logic
STB
Data Latch
State
Control
STB
Y-Decoder
Y-Gating
Low V
CC
Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Cell Matrix
A
0
to A
19
A
-1
5
