MC100EL29
5V ECL Dual Differential
Data and Clock D Flip−Flop
With Set and Reset
Description
The MC100EL29 is a dual master−slave flip flop. The device
features fully differential Data and Clock inputs as well as outputs.
Data enters the master latch when the clock is LOW and transfers to
the slave upon a positive transition on the clock input.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The differential inputs have special circuitry which ensures device
stability under open input conditions. When both differential inputs
are left open the D input will pull down to V
EE
and the D input will
bias around V
CC
/2. The outputs will go to a defined state, however the
state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset
inputs. Note that the Set and Reset inputs cannot both be HIGH
simultaneously.
The 100 Series Contains Temperature Compensation
Features
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SO−20
WB SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100EL29
AWLYYWWG
•
•
•
•
•
•
•
•
•
•
•
•
1100 MHz Flip−Flop Toggle Frequency
580 ps Propagation Delays
Q Output will Default LOW with Inputs Open or at V
EE
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−4.2
V to
−5.7
V
Internal Input Pulldown Resistors on D(s), CLK(s), S(s), and R(s).
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level:
Pb = 1
Pb−Free = 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 313 devices
Pb−Free Package is Available*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
October, 2006
−
Rev. 4
1
Publication Order Number:
MC100EL29/D
MC100EL29
R0
20
V
CC
19
Q0
18
Q0
17
S0
16
S1
15
V
CC
14
Q1
13
Q1
12
V
EE
11
Q
R
D
Q
S
CLK
S
Q
D
Q
R
CLK
1
D0
2
3
4
5
6
7
8
9
10
D0 CLK0 CLK0 V
BB
D1
D1 CLK1 CLK1 R1
* All V
CC
pins are tied together on the die.
Warning: All V
CC
and V
EE
pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC
(Top View)
Table 1. PIN DESCRIPTION
PIN
D0, D0; D1, D1
R0−R1
CLK0, CLK0; CLK1, CLK1
S0−S1
Q0, Q0; Q1, Q1
V
BB
V
CC
V
EE
FUNCTION
ECL Differential Data Inputs
ECL Reset Inputs
ECL Differential Clock Inputs
ECL Set Inputs
ECL Differential Data Outputs
Reference Voltage Output
Positive Supply
Negative Supply
Table 2. TRUTH TABLE
R*
L
L
H
L
H
S*
L
L
L
H
H
D*
L
H
X
X
X
CLK*
Z
Z
X
X
X
Q
L
H
L
H
Undef
Q
H
L
H
L
Undef
Z = LOW to HIGH Transition
* Pins will default LOW when left open.
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb
Pb−Free
0 lfpm
500 lfpm
Standard Board
SOIC−20
SOIC−20
SOIC−20
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
8
−8
6
−6
50
100
±
0.5
−40
to +85
−65
to +150
90
60
30 to 35
265
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC100EL29
Table 4. 100EL SERIES PECL DC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V (Note 1)
−40°C
Symbol
I
EE
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Common Mode Range
(Differential Configuration) (Note 3)
V
PP
< 500 mV
V
PP
≥
500 mV
Input HIGH Current
Input LOW Current
0.5
3915
3170
3835
3190
3.62
Min
Typ
130
35
3995
3305
Max
156
50
4120
3445
4120
3525
3.74
3975
3190
3835
3190
3.62
Min
25°C
Typ
130
35
4045
3295
Max
156
50
4120
3380
4120
3525
3.74
3975
3190
3835
3190
3.62
Min
85°C
Typ
130
35
4050
3295
Max
156
50
4120
3380
4120
3525
3.74
Unit
mA
mA
mV
mV
mV
mV
V
V
1.3
1.5
4.6
4.6
150
0.5
1.2
1.4
4.6
4.6
150
0.5
1.2
1.4
4.6
4.6
150
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V /
−0.5
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and
1 V.
Table 5. 100E SERIES NECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
=
−5.0
V (Note 4)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 5)
Output LOW Voltage (Note 5)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Common Mode Range
(Differential Configuration) (Note 6)
V
PP
< 500 mV
V
PP
≥
500 mV
Input HIGH Current
Input LOW Current
0.5
−1085
−1830
−1165
−1810
−1.38
Min
Typ
35
−1005
−1695
Max
50
−880
−1555
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
25°C
Typ
35
−955
−1705
Max
50
−880
−1620
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
85°C
Typ
35
−955
−1705
Max
50
−880
−1620
−880
−1475
−1.26
Unit
mA
mV
mV
mV
mV
V
V
−3.7
−3.5
−0.4
−0.4
150
0.5
−3.8
−3.6
−0.4
−0.4
150
0.5
−3.8
−3.6
−0.4
−0.4
150
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V /
−0.5
V.
5. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
6. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and
1 V.
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MC100EL29
Table 6. AC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−5.0
V (Note 7)
−40°C
Symbol
fmax
t
PLH
t
PHL
t
S
t
H
t
RR
t
PW
t
JITTER
V
PP
t
r
t
f
Characteristic
Maximum Toggle Frequency
Propagation Delay
to Output
Setup Time
Hold Time
Set/Reset Recovery
Minimum Pulse Width CLK, Set, Reset
Cycle−to−Cycle Jitter
Input Swing (Note 8)
Output Rise/Fall Times Q
(20%
−
80%)
150
280
CLK
S, R
480
480
0
100
100
400
TBD
1000
550
150
280
Min
Typ
TBD
680
700
500
500
0
100
100
400
TBD
1000
550
150
280
Max
Min
25°C
Typ
TBD
700
720
520
520
0
100
100
400
TBD
1000
550
Max
Min
85°C
Typ
TBD
720
740
Max
Unit
GHz
ps
ps
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. V
EE
can vary vary +0.8 V /
−0.5
V.
8. V
PP
(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of
≈40.
Q
Driver
Device
Q
Z
o
= 50
W
D
Receiver
Device
Z
o
= 50
W
50
W
50
W
D
V
TT
V
TT
= V
CC
−
2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
−
Termination of ECL Logic Devices.)
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4
MC100EL29
ORDERING INFORMATION
Device
MC100EL29DW
MC100EL29DWG
MC100EL29DWR2
MC100EL29DWR2G
Package
SOIC−20
SOIC−20
(Pb−Free)
SOIC−20
SOIC−20
(Pb−Free)
Shipping
†
38 Units / Rail
38 Units / Rail
1000 / Tape & Reel
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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