Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order number: MC100ES6130
Rev 1, 5/2004
2.5/3.3V 1:4 PECL Clock Driver
with 2:1 Input MUX
The MC100ES6130 is a 2.5 GHz differential PECL 1:4 fanout buffer. The
ES6130 offers a wide operating range of 2.5 V and 3.3 V and also features a
2:1 input MUX which is ideal for redundant clock switchover applications. This
device also includes a synchronous enable pin that forces the outputs into a
fixed logic state. Enable or disable state is initiated only after the outputs are
in a LOW state to eliminate the possibility of a runt clock pulse.
Features
MC100ES6130
DT SUFFIX
16 LEAD TSSOP PACKAGE
CASE 948F
Freescale Semiconductor, Inc...
•
•
•
•
•
•
•
•
•
2 GHz maximum output frequency
25 ps maximum output-to-output skew
150 ps part-to-part skew
350 ps typical propagation delay
2:1 differential MUX input
2.5 / 3.3 V operating range
LVPECL and HSTL input compatible
16-lead TSSOP package
Temperature range –40°C to +85°C
ORDERING INFORMATION
Device
MC100ES6130DT
MC100ES6130DTR2
Package
TSSOP-16
TSSOP-16
Q0
Q0
1
2
16
15
V
CC
EN
Q
D
Q1
Q1
3
14
IN1
4
13
IN1
1
Q2
Q2
5
0
12
IN0
IN0
6
7
8
11
10
Q3
Q3
IN_SEL
9
V
EE
Figure 1. 16-Lead Pinout (Top View) and Logic Diagram
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC100ES6130
Table 1. Pin Description
Number
1, 2, 3, 4, 5, 6, 7,
8
9
10
Name
Q0 to Q3
Q0 to Q3
V
EE
IN_SEL
Description
LVPECL differential outputs: Terminate with 50Ω to V
CC
–2V. For single-ended applications, terminate the
unused output with 50Ω to V
CC
–2V.
Negative power supply: For LVPECL applications, connect to GND.
LVPECL compatible 2:1 mux input signal select: When IN_SEL is LOW, the IN0 input pair is selected. When
IN_SEL is HIGH, the IN1 input pair is selected. Includes a 75kΩ pulldown. Default state is LOW and IN0 is
selected.
LVPECL, HSTL clock or data inputs. Internal 75kΩ pulldown resistors on IN0 and IN1. Internal 75kΩ pullup
and 75kΩ pulldown resistors on IN0, IN1. IN0, IN1 default condition is V
CC
/2 when left floating. IN0, IN1 default
condition is LOW when left floating.
LVPECL compatible synchronous enable: When EN goes HIGH, Q
OUT
will go LOW and Q
OUT
will go HIGH on
the next LOW input clock transition. Includes a 75kΩ pulldown. Default state is LOW when left floating. The
internal latch is clocked on the falling edge of the input (IN0, IN1).
Positive power supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
11, 12, 13, 14
IN0, IN0
IN1, IN1
EN
15
Freescale Semiconductor, Inc...
16
V
CC
Table 2. Truth Table
1
IN0
L
H
X
X
Z
X
IN1
X
X
L
H
X
Z
IN_SEL
L
L
H
H
L
H
EN
L
L
L
L
H
H
Q
L
H
L
L
L
L
1. Z = HIGH to LOW Transition
X = Don’t Care
Table 3. General Specifications
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
0 LFPM, 16 TSSOP
500 LFPM, 16 TSSOP
Value
75 kΩ
75 kΩ
> 2000 V
> 200 V
> 1500 V
138°C/W
108°C/W
θ
JA
Thermal Resistance (Junction-to-Ambient)
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
MOTOROLA
2
TIMING SOLUTIONS
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC100ES6130
Table 4. Absolute Maximum Ratings
1
Symbol
V
SUPPLY
V
IN
I
out
T
A
T
STG
Power Supply Voltage
Input Voltage
Rating
Conditions
Difference between V
CC
& V
EE
V
CC
– V
EE
≤
3.6 V
Continuous
Surge
Rating
3.9
V
CC
+ 0.3
V
EE
– 0.3
50
100
–40 to +85
–65 to +150
Units
V
V
V
mA
mA
°C
°C
Output Current
Operating Temperature Range
Storage Temperature Range
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5. DC Characteristics
(V
CC
= 0 V, V
EE
= –2.5 V ±5% or V
CC
= 2.5 V ±5%, V
EE
= 0 V)
Freescale Semiconductor, Inc...
Symbol
I
EE
V
OH
V
OL
V
outPP
V
IH
V
IL
V
PP
V
CMR
I
IN
Characteristic
Power Supply Current
Output HIGH Voltage
1
Output LOW Voltage
1
Output Peak-to-Peak Voltage
Input HIGH Voltage
Input LOW Voltage
Differential Input Voltage
2
Differential Cross Point Voltage
3
Input Current
–40°C
Min
Typ
45
V
CC
– 1250
V
CC
– 990
Max
70
V
CC
– 800
V
CC
– 1200
Min
0°C to 85°C
Typ
45
V
CC
– 960
Max
70
V
CC
– 750
Unit
mA
mV
mV
mV
V
CC
– 2000 V
CC
– 1550 V
CC
– 1150 V
CC
– 1925 V
CC
– 1630 V
CC
– 1200
200
V
CC
– 1165
V
CC
– 1810
0.12
V
EE
+ 0.2
V
CC
– 880
200
V
CC
– 1165
V
CC
– 880
V
CC
– 1475
1.3
V
CC
– 1.0
±150
mV
mV
V
V
µA
V
CC
– 1475 V
CC
– 1810
1.3
V
CC
– 1.0
±150
0.12
V
EE
+ 0.2
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
3. V
CMR
(DC) is the cross point of the differential input signal. Functional operation is obtained when the cross point is within the V
CMR
(DC) range
and the input swing lies within the V
PP
(DC) specification.
Table 6. DC Characteristics
(V
CC
= 0 V, V
EE
= –3.8 to 3.135 V or V
CC
= 3.135 to 3.8 V, V
EE
= 0 V)
Symbol
I
EE
V
OH
V
OL
V
outPP
V
IH
V
IL
V
PP
V
CMR
I
IN
Characteristic
Power Supply Current
Output HIGH Voltage
1
Output LOW Voltage
1
Output Peak-to-Peak Voltage
Input HIGH Voltage
Input LOW Voltage
Differential Input Voltage
2
Differential Cross Point Voltage
3
Input Current
–40°C
Min
Typ
48
V
CC
– 1150 V
CC
– 1020
Max
70
V
CC
– 800
V
CC
– 1200
Min
0°C to 85°C
Typ
48
V
CC
– 970
Max
70
V
CC
– 750
Unit
mA
mV
mV
mV
V
CC
– 880
V
CC
– 1475
1.3
V
CC
– 1.1
±150
mV
mV
V
V
µA
V
CC
– 1950 V
CC
– 1620 V
CC
– 1250 V
CC
– 2000 V
CC
– 1680 V
CC
– 1300
200
V
CC
– 1165
V
CC
– 1810
0.12
V
EE
+ 0.2
V
CC
– 880
200
V
CC
– 1165
V
CC
– 1475 V
CC
– 1810
1.3
V
CC
- 1.1
±150
0.12
V
EE
+ 0.2
1. Output termination voltage V
TT
= 0 V for V
CC
= 2.5 V operation is supported but the power consumption of the device will increase.
2. V
PP
(DC) is the minimum differential input voltage swing required to maintain device functionality.
3. V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
(DC) range
and the input swing lies within the V
PP
(DC) specification.
TIMING SOLUTIONS
3
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC100ES6130
Table 7. AC Characteristics
(V
CC
= 0 V, V
EE
= –3.8 V to –2.375 V; V
CC
= 2.375 to 3.8 V, V
EE
= 0 V)
1
–40°C
Symbol
f
max
Characteristic
Min
Maximum Frequency
2
300
340
15
450
25
125
1
200
V
EE
+ 0.2
70
1200
200
Typ
Max
Min
2
300
350
15
450
25
150
1
1200
200
Typ
Max
Min
2
300
350
15
475
25
150
1
1200
V
CC
– 1.2
275
Typ
Max
GHz
ps
ps
ps
ps
mV
V
ps
25°C
85°C
Unit
t
PLH /
t
PHL
Propagation Delay to Output
Differential
CLK to Q, Q
t
SKEW
t
JITTER
V
PP
V
CMR
t
r
/ t
f
Skew
2
Cycle-to-Cycle Jitter
Minimum Input Swing
Differential Cross Point Voltage
Output Rise/Fall Times
(20% – 80% @ 50 MHz)
output-to-output
part-to-part
RMS (1σ)
V
CC
– 1.2 V
EE
+ 0.2
225
70
V
CC
– 1.2 V
EE
+ 0.2
250
70
Freescale Semiconductor, Inc...
1. Measured using a 750 mV source, 50% Duty Cycle clock source. All loading with 50 ohms to V
CC
–2.0V.
2. Skew is measured between outputs under identical transitions.
Figure 1.
Q
Driver
Device
Qb
50Ω
50Ω
D
Receiver
Device
Db
V TT
Figure 2. Typical Termination for Output Driver and Device Evaluation
MOTOROLA
4
TIMING SOLUTIONS
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC100ES6130
OUTLINE DIMENSIONS
TSSOP-16
DT SUFFIX
16-LEAD TSSOP PACKAGE
CASE 948F-01
ISSUE 0
K
0.15 (0.006) T U
S
16X
REF
M
0.10 (0.004)
T U
S
V
S
K
K1
2X
L/2
16
9
J1
B
-U-
SECTION N-N
J
Freescale Semiconductor, Inc...
L
PIN 1
IDENT.
1
8
N
0.25 (0.010)
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
A
-V-
N
F
DETAIL E
M
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
---
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0˚
8˚
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
---
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0˚
8˚
C
0.10 (0.004)
-T-
SEATING
PLANE
-W-
H
D
G
DETAIL E
CASE 948F-01
ISSUE O
DATE 12/20/94
TIMING SOLUTIONS
5
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
