MC100LVEL33
3.3 V ECL
÷4
Divider
The MC100LVEL33 is an integrated
÷4
divider. The LVEL is
functionally equivalent to the EL33 and works from a 3.3 V supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple LVEL33’s in a system.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
Description
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8
1
SOIC−8 NB
D SUFFIX
CASE 751−07
8
1
TSSOP−8
DT SUFFIX
CASE 948R−02
•
630 ps Typical Propagation Delay
•
4.0 GHz Typical Maximum Frequency
•
ESD Protection:
♦
MARKING DIAGRAMS*
8
KVL33
ALYW
G
1
SOIC−8
1
8
KV33
ALYWG
G
•
•
•
•
•
•
•
•
•
> 4 KV Human Body Model
♦
> 200 V Machine Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−3.8
V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity:
♦
Level 1 for SOIC−8
♦
Level 3 for TSSOP−8
♦
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 130 Devices
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
TSSOP−8
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note
AND8002/D.
ORDERING INFORMATION
Device
MC100LVEL33DG
MC100LVEL33DR2G
MC100LVEL33DTG
MC100LVEL33DTR2G
Package
SOIC−8 NB
(Pb-Free)
SOIC−8 NB
(Pb-Free)
TSSOP−8
(Pb-Free)
TSSOP−8
(Pb-Free)
Shipping†
98 Units / Tube
2500Tape & Reel
100 Units / Tube
2500 Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
July, 2016
−
Rev. 6
1
Publication Order Number:
MC100LVEL33/D
MC100LVEL33
Table 1. PIN DESCRIPTION
Reset
1
R
8
V
CC
PIN
CLK*, CLK**
Q, Q
Reset*
V
BB
V
CC
V
EE
FUNCTION
ECL Differential Clock Inputs
ECL Differential Data
÷4
Outputs
ECL Asynch Reset
Reference Voltage Output
Positive Supply
Negative Supply
CLK
2
7
Q
÷4
CLK
3
6
Q
V
BB
4
5
V
EE
* Pins will default LOW when open due to internal 75 kW
resistor to V
EE
** Pins will default to 1/2 V
CC
when open due to internal
resistors: 75 kW to V
EE
and 75 kW to V
CC
Figure 1. Logic Diagram and Pinout Assignment
Table 2. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
< 2 to 3 sec @ 260°C
SOIC−8 NB
SOIC−8 NB
SOIC−8 NB
TSSOP−8
TSSOP−8
TSSOP−8
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
±
0.5
−40
to +85
−65
to +150
190
130
41 to 44
±5%
185
140
41 to 44
±5%
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
MC100LVEL33
Table 3. LVPECL DC CHARACTERISTICS
(V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)-
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
V
PP
<
500 Mv
V
PP
≥
500 mV
Input HIGH Current
Input LOW Current
Other
CLK
0.5
−600
2215
1470
2135
1490
1.92
Min
Typ
33
2295
1605
Max
37
2420
1745
2420
1825
2.04
2275
1490
2135
1490
1.92
Min
25°C
Typ
33
2345
1595
Max
37
2420
1680
2420
1825
2.04
2275
1490
2135
1490
1.92
Min
85°C
Typ
35
2345
1595
Max
39
2420
1680
2420
1825
2.04
Unit
mA
mV
mV
mV
mV
V
V
1.2
1.4
2.9
2.9
150
0.5
−600
1.1
1.3
2.9
2.9
150
0.5
−600
1.1
1.3
2.9
2.9
150
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
Table 4. LVNECL DC CHARACTERISTICS
(V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
V
PP
<
500 Mv
V
PP
≥
500 mV
Input HIGH Current
Input LOW Current
Other
CLK
0.5
−600
−1085
−1830
−1165
−1810
−1.38
Min
Typ
33
−1005
−1695
Max
37
−880
−1555
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
25°C
Typ
33
−955
−1705
Max
37
−880
−1620
−880
−1475
−1.26
−1025
−1810
−1165
−1810
−1.38
Min
85°C
Typ
35
−955
−1705
Max
39
−880
−1620
−880
−1475
−1.26
Unit
mA
mV
mV
mV
mV
V
V
−2.1
−1.9
−0.4
−0.4
150
0.5
−600
−2.2
−2.0
−0.4
−0.4
150
0.5
−600
−2.2
−2.0
−0.4
−0.4
150
mA
mA
I
IH
I
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
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3
MC100LVEL33
Table 5. AC CHARACTERISTICS
(V
CC
= 3.3 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
=
−3.3
V (Note 1))
−40°C
Symbol
f
max
t
PLH
t
PHL
Characteristic
Maximum Toggle Frequency
Propagation Delay
CLK to Q (Diff)
CLK to Q (SE)
Reset to Q
Reset Recovery
Duty Cycle Skew (Note 2)
Cycle-to-Cycle Jitter
Input Voltage Swing
(Differential Configuration)
Output Rise / Fall Times Q (20%−80%)
150
120
0.5
Min
3.4
530
530
500
300
20
< 1.0
1000
320
150
120
0.5
630
655
730
780
700
Typ
Max
Min
3.8
570
570
520
300
20
< 1.0
1000
320
150
120
0.5
25°C
Typ
4.0
670
695
770
820
720
Max
Min
3.8
650
650
580
300
20
< 1.0
1000
320
750
775
850
900
780
85°C
Typ
Max
Unit
GHz
ps
ps
ps
ps
mV
ps
t
RR
t
skew
t
JITTER
V
PP
t
r
t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. V
EE
can vary
±0.3
V.
2. Duty cycle skew is the difference between T
PLH
and T
PHL
.
CLK
RESET
Q
Figure 1. Timing Diagram
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4
MC100LVEL33
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
−
3.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note
AND8020/D
−
Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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5
