MC10137
Universal Decade Counter
The MC10137 is a high speed synchronous counter that can count
up, down, preset, or stop count at frequencies exceeding 100 MHz.
The flexibility of this device allows the designer to use one basic
counter for most applications. The synchronous count feature makes
the MC10137 suitable for either computers or instrumentation.
Three control lines (S1, S2, and Carry In) determine the operation
mode of the counter. Lines S1 and S2 determine one of four
operations; preset (program), increment (count up), decrement (count
down), or hold (stop count). Note that in the preset mode a clock pulse
is necessary to load the counter, and the information present on the
data inputs (D0, D1, D2, and D3) will be entered into the counter.
Carry Out goes low on the terminal count. The Carry Out on the
MC10137 is partially decoded from Q1 and Q2 directly, so in the
preset mode the condition of the Carry Out after the Clock’s positive
excursion will depend on the condition of Q1 and/or Q2. The counter
changes state only on the positive going edge of the clock. Any other
input may change at any time except during the positive transition of
the clock. The sequence for counting out of improper states is as
shown in the State Diagrams.
•
PD = 625 mW typ/pkg (No Load)
•
fcount = 150 MHz typ
•
tpd = 3.3 ns typ (C–Q)
•
= 7.0 ns typ (C–Cout)
•
= 5.0 ns typ (Cin–Cout)
STATE DIAGRAMS
COUNT UP
15
0
1
2
10
12
14
9
8
7
6
3
11
13
5
4
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MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
1
16
PDIP–16
P SUFFIX
CASE 648
1
1
PLCC–20
FN SUFFIX
CASE 775
10137
AWLYYWW
MC10137P
AWLYYWW
MC10137L
AWLYYWW
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
COUNT DOWN
0
1
2
13
7
6
5
3
FUNCTION SELECT TABLE
S1
4
14
10
15
11
S2
L
H
L
H
Operating Mode
Preset (Program)
Increment (Count Up)
Decrement (Count Down)
Hold (Stop Count)
L
12
9
8
L
H
H
DIP PIN ASSIGNMENT
VCC1
2
3
COUT
D3
D2
S2
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC2
Q1
Q0
C
D0
D1
CIN
S1
MC10137L
MC10137P
MC10137FN
CDIP–16
PDIP–16
PLCC–20
25 Units / Rail
25 Units / Rail
46 Units / Rail
ORDERING INFORMATION
Device
Package
Shipping
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
©
Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 6
Publication Order Number:
MC10137/D
MC10137
LOGIC DIAGRAM
S1 9
S2 7
10
Carry In
Q0
T
T
Q0
C
T
J
T
T
Q1
Q1
C
K
T
T
J
T
Q2
Q2
C
J
T
J
T
T
Q3
Q3
C
13
Clock
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
12 D0
14 Q0
11 D1
15 Q1
6 D2
2 Q2
5 D3
3 Q3
4 Carry Out
NOTE:
Flip–flops will toggle when all T inputs are low.
SEQUENTIAL TRUTH TABLE*
INPUTS
S1
L
L
L
L
L
L
L
H
L
H
H
H
S2
L
H
H
H
H
H
H
H
L
L
L
L
D0
H
X
X
X
X
X
X
X
H
X
X
X
D1
H
X
X
X
X
X
X
X
H
X
X
X
D2
H
X
X
X
X
X
X
X
L
X
X
X
D3
L
X
X
X
X
X
X
X
L
X
X
X
Carry
In
X
L
L
L
L
H
H
X
X
L
L
L
Clock
**
H
H
H
H
H
L
H
H
H
H
H
H
Q0
H
L
H
L
H
H
H
H
H
L
H
L
Q1
H
L
L
L
L
L
L
L
H
H
L
L
OUTPUTS
Q2
H
L
L
L
L
L
L
L
L
L
L
L
Q3
L
H
H
L
L
L
L
L
L
L
L
L
Carry
Out
H
H
L
H
H
H
H
H
H
H
H
L
* Truth table shows logic states assuming inputs vary in sequence shown from top to bottom.
** A clock H is defined as a clock input transition from a low to a high logic level.
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2
MC10137
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
Test
8
5,6,11,12
7
9,10
13
All
14
(NO
TAG)
–30°C
Min
Max
165
350
425
390
460
0.5
–1.060
–1.890
–1.080
–1.655
–0.890
–1.675
0.5
–0.960
–1.850
–0.980
Min
+25°C
Typ
120
Max
150
220
265
245
290
0.3
–0.810
–1.650
+85°C
Min
Max
165
220
265
245
290
Unit
mAdc
µAdc
Characteristic
Power Supply Drain Current
Input Current
Symbol
IE
IinH
IinL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Switching Times
Logic 1
Logic 0
Logic 1
Logic 0
(50Ω Load)
t13+14+
t13+14–
t13+4+
t13+4–
t10–4–
t10+4+
t12+13+
t12–13+
t9+13+
t7+13+
t10–13+
t13+10+
t13+12+
t13+12–
t13+9+
t13+7+
t13+10–
t10+13+
fcountup
fcountdown
t4+
t14+
t4–
t14–
VOH
VOL
VOHA
VOLA
µAdc
–0.700
–1.615
Vdc
Vdc
Vdc
–1.595
Vdc
ns
–0.890
–1.825
–0.910
14
(NO
TAG)
14
(NO
TAG)
14
(NO
TAG)
–1.630
Propagation Delay Clock Input
14
14
4
4
4
(NO
TAG)
4
14
14
14
14
14
14
14
14
14
14
14
14
14
14
4
14
4
14
0.8
0.8
2.0
2.0
1.6
1.6
3.5
3.5
7.5
7.5
4.5
–1.0
0
0
–2.5
–2.5
–1.6
4.0
125
125
0.9
0.9
0.9
0.9
4.8
4.8
10.9
10.9
7.4
7.4
1.0
1.0
2.5
2.5
1.6
1.6
3.5
3.5
7.5
7.5
3.7
–1.0
0
0
–2.5
–2.5
–1.6
3.1
125
125
3.3
3.3
7.0
7.0
5.0
5.0
4.5
4.5
10.5
10.5
6.9
6.9
1.1
1.1
2.4
2.4
1.9
1.9
3.5
3.5
7.5
7.5
4.5
–1.0
0
0
–2.5
–2.5
–1.6
4.0
5.0
5.0
11.5
11.5
7.5
7.5
Carry In to Carry Out
Setup Time
Data Inputs
Select Inputs
Carry In Input
Hold Time
Data Inputs
Select Inputs
Carry In Input
Counting Frequency
Rise Time
Fall Time
(20 to 80%)
(20 to 80%)
150
150
2.0
2.0
2.0
2.0
3.3
3.3
3.3
3.3
125
125
1.1
1.1
1.1
1.1
3.5
3.5
3.5
3.5
MHz
ns
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1. Individually apply VILmin to pin under test.
VIH
appears at clock input (Pin 13).
2. Measure output after clock pulse
VIL
3. Before test set Q1 and Q2 outputs to a logic low.
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3
MC10137
ELECTRICAL CHARACTERISTICS
(continued)
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
–30°C
+25°C
+85°C
Pin
Under
Test
8
5,6,11,12
7
9,10
13
All
14
(NO
TAG)
VIHmax
–0.890
–0.810
–0.700
VILmin
–1.890
–1.850
–1.825
VIHAmin
–1.205
–1.105
–1.035
VILAmax
–1.500
–1.475
–1.440
VEE
–5.2
–5.2
–5.2
(VCC)
Gnd
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
+2.0 V
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
5,6,11,12
7
9,10
13
Note
NO TAG
12
7, 9
7, 9
7, 9
7, 9
+1.11V
+0.31V
Pulse In
13
13
13
13
13
13
7, 9
7, 9
10
10
12, 13
12, 13
9, 13
7, 13
7
7
9
9
7, 9
7, 9
10, 13
10, 13
12, 13
12, 13
9, 13
7, 13
7
7
7
9
7
7
7
7
9
9
10, 13
10, 13
13
13
13
13
13
13
12
12
Pulse Out
14
14
4
4
4
4
14
14
14
14
14
14
14
14
14
14
14
14
14
14
4
14
4
14
VILmin
VIHAmin
VILAmax
VEE
8
8
8
8
8
8
8
8
8
8
–3.2 V
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
Characteristic
Power Supply Drain Current
Input Current
Symbol
IE
IinH
IinL
Output Voltage
Output Voltage
Threshold Voltage
Threshold Voltage
Switching Times
Propagation Delay
Logic 1
Logic 0
Logic 1
Logic 0
(50Ω Load)
Clock Input
t13+14+
t13+14–
t13+4+
t13+4–
t10–4–
t10+4+
t12+13+
t12–13+
t9+13+
t7+13+
t10–13+
t13+10+
t13+12+
t13+12–
t13+9+
t13+7+
t13+10–
t10+13+
fcountup
fcountdown
(20 to 80%)
(20 to 80%)
t4+
t14+
t4–
t14–
VOH
VOL
VOHA
VOLA
14
(NO
TAG)
14
(NO
TAG)
14
(NO
TAG)
14
14
4
4
4
(NO TAG)
4
14
14
14
14
14
14
14
14
14
14
14
14
14
14
4
14
4
14
12
7
7
7
7
Carry In to Carry Out
Setup Time
Data Inputs
Select Inputs
Carry In Inputs
Hold Time
Data Inputs
Select Inputs
Carry In Inputs
Counting Frequency
Rise Time
Fall Time
1. Individually test each input; apply VILmin to pin under test.
VIH
appears at clock input (Pin 13).
2. Measure output after clock pulse
VIL
3. Before test set all Q outputs to a logic high.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
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4
MC10137
Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25
°
C
Carry In
(b)
(a) is the minimum time to wait after the
counter has been enabled to clock it.
(a)
Clock
(b) is the minimum time before the counter
has been disabled that it may be clocked.
(c) is the minimum time before the counter
is enabled that a clock pulse may be
applied with no effect on the state of the
counter.
(d) is the minimum time to wait after the
counter is disabled that a clock pulse may
be applied with no effect in the state of the
counter.
(b) and (c) may be negative numbers.
(d)
Clock
Vin
NOTE:
tsetup is the minimum time before the positive
transition of the clock pulse (C) that information must
be present at the input D or S.
thold is the minimum time after the positive
transition of the clock pulse (C) that information must
remain unchanged at the input D or S.
Input Pulse
t+ = t– = 2.0
±0.2
ns
(20 to 80%)
Clock Input
VCC1 = VCC2 = +2.0 Vdc
Vout
Carry in
(c)
Coax
25
µF
0.1
µF
Coax
1
Cin
C
D0
D1
D2
D3
+1.11 V
TPin
S1
S2
+0.31 V
8
16
Q0
Q1
Q2
Q3
Cout
TPout
Clock
50%
tC+Q+
tC+Q–
Q Output
80%
50%
20%
tQ+
tQ–
+1.11 V
VEE = –3.2 Vdc
0.1
µF
C
50%
+0.31 V
thold H
thold L
50%
tsetup H
tsetup L
50-ohm termination to ground lo-
cated in each scope channel input.
All input and output cables to the
scope are equal lengths of 50-ohm
coaxial cable. Wire length should be
< 1/4 inch from TPin to input pin and
TPout to output pin.
Unused outputs are connected to a
50-ohm resistor to ground.
D or S
Q
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5
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