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Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
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by MC145162/D
60 MHz and 85 MHz Universal
Programmable Dual PLL
Frequency Synthesizers
CMOS
The MC145162 is a dual phase–locked loop (PLL) frequency synthesizer
especially designed for CT–1 cordless phone applications worldwide. This
frequency synthesizer is also for any product with a frequency operation at
60 MHz or below.
The MC145162–1 is a high frequency derivative of the MC145162, for
products with operating frequencies of 85 MHz or below.
The device features fully programmable receive, transmit, reference, and
auxiliary reference counters accessed through an MCU serial interface. This
feature allows this device to operate in any CT–1 cordless phone application.
The device consists of two independent phase detectors for transmit and
receive loops. A common reference oscillator, driving two independent
reference frequency counters, provides independent reference frequencies for
transmit and receive loops. The auxiliary reference counter allows the user to
select an additional reference frequency for receive and transmit loops if
required.
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Operating Voltage Range: 2.5 to 5.5 V
Operating Temperature Range: – 40 to + 75°C
Operating Power Consumption: 3.0 mA @ 2.5 V
Maximum Operating Frequency:
MC145162 — 60 MHz @ 200 mV p–p, VDD = 2.5 V
MC145162–1 — 85 MHz @ 250 mV p–p, VDD = 2.5 V
Three or Four Pins Used for Serial MCU Interface
Built–In MCU Clock Output with Frequency of Reference Oscillator 3/
Power Saving Mode Controlled by MCU
Lock Detect Signal
On–Chip Reference Oscillator Supports External Crystals to 16.0 MHz
Reference Frequency Counter Division Range: 16 to 4095
Auxiliary Reference Frequency Counter Division Range: 16 to 16,383
Transmit Counter Division Range: 16 to 65,535
Receive Counter Division Range: 16 to 65,535
MC145162
MC145162-1
P SUFFIX
PLASTIC DIP
CASE 648
1
16
16
1
Freescale Semiconductor, Inc...
D SUFFIX
SOG PACKAGE
CASE 751B
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
ORDERING INFORMATION
MC145162P
MC145162D
MC145162P1
MC145162D1
Plastic DIP
SOG Package
Plastic DIP
SOG Package
PIN ASSIGNMENT
CLK
ADin
Din
ENB
MCUCLK
VSS
OSCin
OSCout
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
LD
TxPDout
fin–T
TxPS/fTx
VDD
RxPS/FRx
RxPDout
fin–R
4
REV 3.1
2/98
©
Motorola, Inc. 1998
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MC145162•MC145162–1
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BLOCK DIAGRAM
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
OSCin
7
12–BIT PROGRAMMABLE
REFERENCE COUNTER
A
B
C
fR2
D
fR1
4
25
8
OSCout
14–BIT PROGRAMMABLE
AUXILIARY REFERENCE
COUNTER
MCUCLK
5
3/
4
12–BIT SHIFT
REGISTER
14–BIT SHIFT
REGISTER
TRANSMIT
SELECT
Tx
PHASE
DETECTOR
15
TxPDout
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ADin
2
1
3
4
13
11
16–BIT SHIFT REGISTER
MCU INTERFACE PROGRAMMING
MODE CONTROL
CONTROL REGISTER
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CLK
Din
ENB
TxPS/fTx
RxPS/fRx
16
LD
fin–T
14
16–BIT Tx PROGRAMMABLE
COUNTER
RECEIVE
SELECT
Rx
PHASE
DETECTOR
10
RxPDout
16–BIT SHIFT REGISTER
fin–R
9
16–BIT Rx PROGRAMMABLE
COUNTER
VDD = PIN 12
VSS = PIN 6
MC145162•MC145162–1
2
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MOTOROLA
Freescale Semiconductor, Inc.
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Rating
Value
Unit
ARCHIVED BY FREESCALE SEMICONDUCTOR,
+ 6.0
2005
VDD
DC Supply Voltage
– 0.5 to
INC.
V
Vin
Iin, Iout
IDD, ISS
Tstg
Input Voltage, All Inputs
DC Current Drain Per Pin
DC Current Drain VDD or VSS Pins
Storage Temperature Range
– 0.5 to VDD + 0.5
10
30
– 65 to + 150
V
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid application of any voltage
higher than maximum rated voltages to this
high–impedance circuit. For proper operation,
Vin and Vout should be constrained to the range
VSS
≤
(Vin or Vout)
≤
VDD.
Unused pins must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, TA = 25°C)
Guaranteed Limit
Symbol
S b l
Characteristic
Ch
i i
Power Supply Voltage Range
Output Voltage
(Iout = 0)
(Vin = VDD or 0)
Input Voltage
(Vout = 0.5 V or VDD – 0.5 V)
0 Level
1 Level
0 Level
1 Level
Output Current
(Vout = 2.2 V)
(Vout = 5.0 V)
(Vout = 0.3 V)
(Vout = 0.5 V)
Input Current
(Vin = 0)
Source
Sink
OSCin, fin–T, fin–R
ADin, CLK, Din, ENB
IIH
(Vin = VDD – 0.5)
OSCin, fin–T, fin–R
ADin, CLK, Din, ENB
IOZ
Cin
Cout
IDD(stdby)
IDD
Three–State Leakage Current (Vout = 0 V or 5.5 V)
Input Capacitance
Output Capacitance
Standby Current
(All Counters are in Power–Down Mode with Oscillator On)
Operating Current
MC145162: 200 mV p–p input at fin–T and fin–R = 60 MHz
MC145162–1: 250 mV p–p input at fin–T and fin–R = 85 MHz
with OSC = 10.24 MHz
VDD
—
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
5.5
—
—
2.5
5.5
2.5
5.5
Min
2.5
—
—
2.45
5.45
—
—
1.75
3.85
– 0.18
– 0.55
0.18
0.55
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
5.5
0.1
0.1
—
—
0.75
1.65
—
—
—
—
—
—
– 30
– 66
– 1.0
– 1.0
30
66
5.0
5.0
±
100
8.0
8.0
0.3
1.5
3.0
10
nA
pF
pF
mA
mA
µA
mA
V
Unit
U i
V
V
Freescale Semiconductor, Inc...
VDD
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005
VOL
VOH
VIL
VIH
IOH
IOL
IIL
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MC145162•MC145162–1
3
Freescale Semiconductor, Inc.
SWITCHING CHARACTERISTICS
(TA = 25°C, CL = 50 pF)
ARCHIVED BY FREESCALE SEMICONDUCTOR,
Symbol
S b l
Characteristic
Ch
i i
tTLH
tTHL
tr, tf
tw
fmax
Output Rise Time
Output Fall Time
Input Rise and Fall Time
Input Pulse Width
Input Frequency
Input = Sine Wave @
≥
200 mV p–p
for MC145162
Input = Sine Wave @
≥
250 mV p–p
for MC145162–1
Minimum Start–Up Time
Setup Time
Hold Time
Recovery Time
Setup Time
Hold Time
Phase Detector Frequency
Output Clock Frequency
(OSCin
3)
Figure
INC. 2005
No.
1
1
Guaranteed Limit
VDD
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5 – 5.5
2.5 – 5.5
2.5 – 5.5
Min
—
—
—
—
—
—
80
60
—
—
—
Max
200
100
200
100
5.0
4.0
—
—
16
60
85
10
ms
ns
ns
ns
ns
ns
kHz
MHz
Unit
U i
ns
ns
µs
ns
MHz
OSCin
CLK and ENB
OSCin
fin–R, fin–T
fin–R, fin–T
2
3
Freescale Semiconductor, Inc...
tst
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tsu
th
trec
tsu1
th1
f
fMCUCLK
DATA to CLK
ENB to CLK
CLK to DATA
ENB to CLK
ENB to CLK
CLK to ENB
5
5
5
4
4
2.5
5.5
3.0
5.0
3.0
5.0
2.5 – 5.5
2.5 – 5.5
100
200
80
40
80
40
80
600
dc
—
—
—
—
—
—
—
—
12.5
5.33
B
MCUCLK
dc
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Freescale Semiconductor, Inc.
SWITCHING WAVEFORMS
THL
TLH
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
OSC , r
2005
CLK,
ANY
OUTPUT
90%
10%
in
fin–T, fin–R
t
t
t
tf
90%
10%
Figure 1.
Figure 2.
tw
ENB, CLK
50%
ADin,
Din
50%
VSS
tsu
th
VDD
VDD
Figure 3.
Freescale Semiconductor, Inc...
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CLK
VDD
CLK
FIRST
CLK
tsu1
ENB
VSS
LAST
CLK
th1
VSS
ENB
VDD
50%
LAST
CLK
FIRST
CLK
trec
50%
VSS
tsu
VDD
VSS
PREVIOUS
DATA
LATCHED
Figure 4. ENB High During Serial Transfer
Figure 5. ENB Low During Serial Transfer
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MC145162•MC145162–1
5
