MC14526B
Presettable 4-Bit Down
Counters
The MC14526B binary counter is constructed with MOS P−channel
and N−channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
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MARKING
DIAGRAMS
MC14526BCP
AWLYYWWG
1
PDIP−16
1
P SUFFIX
CASE 648
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Logic Edge−Clocked Design: Incremented on Positive Transition of
•
•
•
•
Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Rating
Symbol
V
DD
V
in
,
V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Value
−0.5
to +18.0
−0.5
to V
DD
+ 0.5
±10
500
−55
to +125
−65
to +150
260
Unit
V
V
mA
mW
°C
°C
°C
14526B
AWLYWWG
1
SOIC−16 WB
DW SUFFIX
CASE 751G
1
MAXIMUM RATINGS
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 7
1
Publication Order Number:
MC14526B/D
MC14526B
FUNCTION TABLE
Inputs
Clock
X
X
X
X
L
H
H
Reset
H
H
H
L
L
L
L
L
L
L
Inhibit
X
X
X
X
H
L
L
Preset
Enable
L
H
X
H
L
L
L
L
L
L
Cascade
Feedback
L
L
H
X
X
X
L
L
L
L
Output
“0”
L
H
H
L
L
L
L
L
L
L
Resulting
Function
Asynchronous reset*
Asynchronous reset
Asynchronous reset
Asynchronous preset
Decrement inhibited
Decrement inhibited
No change** (inactive edge)
No change** (inactive edge)
Decrement**
Decrement**
X = Don’t Care
NOTES:
** Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.
PIN DESCRIPTIONS
other than all zeroes, the “0” output is valid after the rising
Preset Enable (Pin 3) —
If Reset is low, a high level on the
edge of Preset Enable (when Cascade Feedback is high). See
Preset Enable input asynchronously loads the counter with
the Function Table.
the programmed values on P0, P1, P2, and P3.
Cascade Feedback (Pin 13) —
If the Cascade Feedback
Inhibit (Pin 4) —
A high level on the Inhibit input pre−
input is high, a high level is generated at the “0” output when
vents the Clock from decrementing the counter. With Clock
the count is all zeroes. If Cascade Feedback is low, the “0”
(pin 6) held high, Inhibit may be used as a negative edge clock
output depends on the Preset Enable input level. See the
input.
Function Table.
Clock (Pin 6) —
The counter decrements by one for each
P0, P1, P2, P3 (Pins 5, 11, 14, 2) —
These are the preset
rising edge of Clock. See the Function Table for level
data inputs. P0 is the LSB.
requirements on the other inputs.
Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) —
These are the
Reset (Pin 10) —
A high level on Reset asynchronously
synchronous counter outputs. Q0 is the LSB.
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is
V
SS
(Pin 8) —
The most negative power supply potential.
high, causes the “0” output to go high.
“0” (Pin 12) —
The “0” (Zero) output issues a pulse one
This pin is usually ground.
clock period wide when the counter reaches terminal count
V
DD
(Pin 16) —
The most positive power supply potential.
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and
V
DD
may range from 3.0 to 18 V with respect to V
SS
.
Preset Enable is low. When presetting the counter to a value
STATE DIAGRAM
MC14526B
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
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2
MC14526B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
Characteristic
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3, 4)
(Dynamic plus Quiescent, Per Package)
(C
L
= 50 pF on all outputs, all buffers
switching)
“0” Level
Symbol
V
OL
Vdc
5.0
10
15
−55°C
Min
−
−
−
Max
0.05
0.05
0.05
Min
−
−
−
25°C
Typ
(Note 2)
0
0
0
Max
0.05
0.05
0.05
125°C
Min
−
−
−
Max
0.05
0.05
0.05
Unit
Vdc
“1” Level
“0” Level
V
OH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“1” Level
“0” Level
V
IL
Vdc
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
“1” Level
“0” Level
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
“1” Level
Source
I
OH
5.0
5.0
10
15
5.0
10
15
15
−
5.0
10
15
5.0
10
15
−3.0
−0.64
−1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±
0.1
−
5.0
10
20
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
−
−
−
−
−
−
−
±
0.1
7.5
5.0
10
20
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±
1.0
−
150
300
600
mAdc
Sink
I
OL
mAdc
I
in
C
in
mAdc
pF
mAdc
I
T
= (1.7
mA/kHz)
f + I
DD
I
T
= (3.4
mA/kHz)
f + I
DD
I
T
= (5.1
mA/kHz)
f + I
DD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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3
MC14526B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(C
L
= 50 pF, T
A
= 25_C) (Note 5)
Characteristic
Symbol
V
DD
5.0
10
15
Min
−
−
−
Typ
(Note 6)
100
50
40
Max
200
100
80
Unit
ns
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
(Figures 4, 5)
Propagation Delay Time (Inhibit Used as Negative
Edge Clock)
Clock or Inhibit to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 465 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 135 ns
Clock or Inhibit to “0”
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 155 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 87 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
Propagation Delay Time
Pn to Q
Propagation Delay Time
Reset to Q
Propagation Delay Time
Preset Enable to “0”
Clock or Inhibit Pulse Width
t
PLH
,
t
PHL
(Figures 4, 5, 6)
ns
5.0
10
15
5.0
10
15
t
PLH
,
t
PHL
(Figures 4, 7)
t
PHL
(Figure 8)
t
PHL
,
t
PLH
(Figures 4, 9)
t
w
(Figures 5, 6)
Clock Pulse Frequency (with PE = low)
f
max
(Figures 4, 5, 6)
Clock or Inhibit Rise and Fall Time
t
r
,
t
f
(Figures 5, 6)
t
su
(Figure 1)
t
h
(Figure 2)
t
w
(Figure 3)
Reset Pulse Width
t
w
(Figure 8)
Reset Removal Time
t
rem
(Figure 8)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
250
100
80
−
−
−
−
−
−
90
50
40
30
30
30
250
100
80
350
250
200
10
20
30
550
225
160
240
130
100
260
120
100
250
110
80
220
100
80
125
50
40
2.0
5.0
6.6
−
−
−
40
15
10
– 15
–5
0
125
50
40
175
125
100
– 110
– 30
– 20
1100
450
320
480
260
200
520
240
200
500
220
160
440
200
160
−
−
−
1.5
3.0
4.0
15
5
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
MHz
ms
Setup Time
Pn to Preset Enable
Hold Time
Preset Enable to Pn
Preset Enable Pulse Width
ns
ns
ns
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14526B
V
OH
V
DD
= -V
GS
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
Q3
“0”
EXTERNAL
POWER
SUPPLY
I
OH
V
DD
= V
GS
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
Q3
“0”
EXTERNAL
POWER
SUPPLY
I
OL
V
OL
V
SS
V
SS
Figure 1. Typical Output Source
Characteristics Test Circuit
Figure 2. Typical Output Sink
Characteristics Test Circuit
V
DD
CF
PE
P0
P1
P2
P3
RESET
INHIBIT
CLOCK
Q0
Q1
Q2
Q3
“0”
V
SS
PULSE
GENERATOR
C
L
C
L
C
L
DEVICE
UNDER
TEST
20 ns
C
L
C
L
Q or “0”
C
L
*
TEST POINT
20 ns
CLOCK
50%
V
DD
90%
10%
V
SS
VARIABLE
50% DUTY CYCLE
WIDTH
*Includes all probe and jig capacitance.
Figure 3. Power Dissipation
Figure 4. Test Circuit
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