MC68020
MC68EC020
MICROPROCESSORS
USER’S MANUAL
First Edition
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an
Equal Opportunity/Affirmative Action Employer.
© MOTOROLA INC., 1992
PREFACE
The
M68020 User’s Manual
describes the capabilities, operation, and programming of the
MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32-
bit, second-generation, enhanced embedded microprocessor.
Throughout this manual, “MC68020/EC020” is used when information applies to both the
MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when
information applies only to the MC68020 or MC68EC020, respectively.
For detailed information on the MC68020 and MC68EC020 instruction set, refer to
M68000PM/AD,
M68000 Family Programmer’s Reference Manual.
This manual consists of the following sections:
Section 1
Section 2
Section 3
Section 4
Section 5
Section 6
Section 7
Section 8
Section 9
Section 10
Section 11
Appendix A
Introduction
Processing States
Signal Description
On-Chip Cache Memory
Bus Operation
Exception Processing
Coprocessor Interface Description
Instruction Execution Timing
Applications Information
Electrical Characteristics
Ordering Information and Mechanical Data
Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire
Bus Arbitration Protocol
NOTE
In this manual,
assert
and
negate
are used to specify forcing a
signal to a particular state. In particular,
assertion
and
assert
refer to a signal that is active or true;
negation
and
negate
indicate a signal that is inactive or false. These terms are used
independently of the voltage level (high or low) that they
represent.
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SECTION 1: OVERVIEW
UM Rev 1
TABLE OF CONTENTS
Paragraph
Number
Title
Section 1
Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.6
1.7
Features ..................................................................................................1-2
Programming Model ................................................................................1-4
Data Types and Addressing Modes Overview ........................................1-8
Instruction Set Overview ......................................................................... 1-10
Virtual Memory and Virtual Machine Concepts ....................................... 1-10
Virtual Memory .................................................................................... 1-10
Virtual Machine .................................................................................... 1-12
Pipelined Architecture .............................................................................1-12
Cache Memory ........................................................................................1-13
Section 2
Processing States
2.1
2.1.1
2.1.2
2.1.3
2.2
2.3
2.3.1
2.3.2
Privilege Levels ....................................................................................... 2-2
Supervisor Privilege Level ...................................................................2-2
User Privilege Level .............................................................................2-3
Changing Privilege Level ..................................................................... 2-3
Address Space Types .............................................................................2-4
Exception Processing.............................................................................. 2-5
Exception Vectors ................................................................................2-5
Exception Stack Frame .......................................................................2-6
Section 3
Signal Description
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
MOTOROLA
Page
Number
Signal Index ............................................................................................3-2
Function Code Signals (FC2–FC0) ......................................................... 3-2
Address Bus (A31–A0, MC68020)(A23–A0, MC68EC020) .................... 3-2
Data Bus (D31–D0) .................................................................................3-2
Transfer Size Signals (SIZ1, SIZ0) .........................................................3-2
Asynchronous Bus Control Signals .........................................................3-4
Interrupt Control Signals..........................................................................3-5
Bus Arbitration Control Signals ............................................................... 3-6
Bus Exception Control Signals ................................................................3-6
Emulator Support Signal .........................................................................3-7
Clock (CLK) ............................................................................................. 3-7
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SECTION 1: OVERVIEW
UM Rev.1.0
TABLE OF CONTENTS (Continued)
Paragraph
Number
3.12
3.13
Title
Page
Number
Power Supply Connections ..................................................................... 3-7
Signal Summary...................................................................................... 3-8
Section 4
On-Chip Cache Memory
4.1
4.2
4.3
4.3.1
4.3.2
On-Chip Cache Organization and Operation .......................................... 4-1
Cache Reset ........................................................................................... 4-3
Cache Control ......................................................................................... 4-3
Cache Control Register (CACR) .........................................................4-3
Cache Address Register (CAAR) ........................................................ 4-4
Section 5
Bus Operation
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.2
5.4.3
5.5
5.5.1
viii
Bus Transfer Signals............................................................................... 5-1
Bus Control Signals ............................................................................. 5-2
Address Bus ........................................................................................ 5-3
Address Strobe .................................................................................... 5-3
Data Bus.............................................................................................. 5-3
Data Strobe ......................................................................................... 5-4
Data Buffer Enable .............................................................................. 5-4
Bus Cycle Termination Signals............................................................ 5-4
Data Transfer Mechanism....................................................................... 5-5
Dynamic Bus Sizing ............................................................................ 5-5
Misaligned Operands........................................................................... 5-14
Effects of Dynamic Bus Sizing and Operand Misalignment ................ 5-20
Address, Size, and Data Bus Relationships ........................................ 5-21
Cache Interactions .............................................................................. 5-22
Bus Operation ..................................................................................... 5-24
Synchronous Operation with
DSACK1/DSACK0
............................... 5-24
Data Transfer Cycles ..............................................................................5-25
Read Cycle .......................................................................................... 5-26
Write Cycle .......................................................................................... 5-33
Read-Modify-Write Cycle..................................................................... 5-39
CPU Space Cycles ................................................................................. 5-44
Interrupt Acknowledge Bus Cycles ......................................................5-45
Interrupt Acknowledge Cycle—Terminated Normally ...................... 5-45
Autovector Interrupt Acknowledge Cycle ......................................... 5-48
Spurious Interrupt Cycle .................................................................. 5-48
Breakpoint Acknowledge Cycle ........................................................... 5-50
Coprocessor Communication Cycles .................................................. 5-53
Bus Exception Control Cycles................................................................. 5-53
Bus Errors ........................................................................................... 5-55
M68020 USER’S MANUAL
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SECTION 1: OVERVIEW
UM Rev 1
TABLE OF CONTENTS (Continued)
Paragraph
Number
5.5.2
5.5.3
5.5.4
5.6
5.7
5.7.1
5.7.1.1
5.7.1.2
5.7.1.3
5.7.1.4
5.7.2
5.7.2.1
5.7.2.2
5.7.2.3
5.8
Title
Page
Number
Retry Operation ...................................................................................5-56
Halt Operation......................................................................................5-60
Double Bus Fault ................................................................................. 5-60
Bus Synchronization................................................................................5-62
Bus Arbitration .........................................................................................5-62
MC68020 Bus Arbitration ....................................................................5-63
Bus Request (MC68020) .................................................................5-66
Bus Grant (MC68020) ......................................................................5-66
Bus Grant Acknowledge (MC68020) ...............................................5-66
Bus Arbitration Control (MC68020) ..................................................5-67
MC68EC020 Bus Arbitration ...............................................................5-70
Bus Request (MC68EC020) ............................................................5-71
Bus Grant (MC68EC020) .................................................................5-71
Bus Arbitration Control (MC68EC020) .............................................5-73
Reset Operation ......................................................................................5-76
Section 6
Exception Processing
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.2
6.2.1
6.2.2
6.2.3
6.3
6.4
Exception Processing Sequence ............................................................6-1
Reset Exception...................................................................................6-4
Bus Error Exception .............................................................................6-4
Address Error Exception...................................................................... 6-6
Instruction Trap Exception ...................................................................6-6
Illegal Instruction and Unimplemented Instruction Exceptions ............ 6-7
Privilege Violation Exception ............................................................... 6-8
Trace Exception ...................................................................................6-9
Format Error Exception .......................................................................6-10
Interrupt Exceptions .............................................................................6-11
Breakpoint Instruction Exception ......................................................... 6-17
Multiple Exceptions..............................................................................6-17
Return from Exception .........................................................................6-19
Bus Fault Recovery .................................................................................6-21
Special Status Word (SSW).................................................................6-21
Using Software to Complete the Bus Cycles .......................................6-23
Completing the Bus Cycles with RTE ..................................................6-24
Coprocessor Considerations ...................................................................6-25
Exception Stack Frame Formats .............................................................6-25
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