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MC68A00P

8-BIT MICROPROCESSING UNIT (MPU)

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:Motorola ( NXP )

厂商官网:https://www.nxp.com

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Motorola ( NXP )
零件包装代码
DIP
包装说明
DIP, DIP40,.6
针数
40
Reach Compliance Code
unknown
地址总线宽度
16
位大小
8
边界扫描
NO
最大时钟频率
1.5 MHz
外部数据总线宽度
8
格式
FIXED POINT
集成缓存
NO
JESD-30 代码
R-PDIP-T40
JESD-609代码
e0
长度
52.07 mm
低功率模式
YES
DMA 通道数量
外部中断装置数量
2
串行 I/O 数
端子数量
40
片上数据RAM宽度
最高工作温度
70 °C
最低工作温度
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP40,.6
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
RAM(字数)
0
座面最大高度
5.08 mm
速度
1.5 MHz
最大供电电压
5.25 V
最小供电电压
4.75 V
标称供电电压
5 V
表面贴装
NO
技术
NMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
15.24 mm
uPs/uCs/外围集成电路类型
MICROPROCESSOR
文档预览
MCWOO
I
i
8-BIT MICROPROCESSING
UNIT (MPU)
I
The MC6800 is a monolithic 8-bit microprocessor forming the central
control function for Motorola’s M68~ family. Compatible with TTL, the
MC6B~, as with all M6800 system parts, requires only one + 5.O-volt
power supply, and no external TTL devices for bus interface.
The MC6800 is capable of addressing 64K bytes of memory with its
16-bit address lines. The 8-bit data bus is bidirectional as well as three-
state, making direct memory addressing and multiprocessing applica-
tions realizable.
q
8-Bit Parallel Processing
q
Bidirectional
Data Bus
– Variable Length
Indexed,
.
.
16-Bit Address Bus – WK Bytes of Addressing
Seven Addressing Modes – Direct, Relative, Immediate,
Extended, Implied and Accumulator
q
72 Instructions
,>:
,,*!.
“)!.IC,[
. Vectored Restart
.}. ‘.*$
,,2:+.(
~
‘~”‘%1
*F.
. Maskable Interrupt Vector
~
..!’.
. Separate Non-Maskable Interrupt – Internal Registers Saved i#’’::$$
, +, ~. ,{).
~,
,)i
.Y,:>, .,,,!,.
-,,,....
Stack
....
*: ,.. ‘is
. Six Internal Registers – Two Accumulators, Index Regist~#?Y’:Y’
Program Counter, Stack Pointer and Condition Code Re~@te~
q
Direct Memory Addressing (D MA) and Multiple P~@$esso’r
.:;.!,.,,>s,-.
Capability
,“ ., . .+
,.,
‘ -->,
*V,1’.- ,,:+~..,
\>>>., **.
q
Simplified Clocking Characteristics
‘~:?iii
...*”,+< *
,,:+,..,
‘.~;:),t.{t,.
. Clock Rates as High as 2.0 MHz
,~>
*:;.>
q
Simple Bus Interface Without TTL
,$~~~~i$~’
q
Variable Length Stack
q
Halt and Single Instruction
uu. -
SUFFIX
CERAMIC PACKAGE
CASE 715
PIN ASSIGNMENT
Vss[
HALT[
10
2
~
JRESET
39 ]TSC
38 ]N. C.
37
Executlo*k$~~$bility
,.*. .\
~
~$$~
‘;:$*Y*:,F
. .., .it~
,.,.$,.>.
‘i,\,.*>
& ‘~~$
..,.
,{,
,:&f*, ~<~’
>
,>$ $$:$
.~~ ~:
...
~+~,‘
\*:,.:
,*..
.+~’
;..
\,\<\!
., \.J.*
.+,t~
INFORMATION
@l [ 3
KQ [ 4
342
VMA [ 5
m[
6
36 ]DBE
35 ]N, C.
34 ]Rl~
33 ] DO
32 ]Dl
31 ] D2
30 ] D3
29 ] D4
28 ] D5
27 ] D6
26 ] D7
25 ]A15
24 ]A14
23 JA13
22 ]A12
21 Jvss
w<,
.-1. $,)
..
,,,~~&Y@’DERING
BA [ 7
Package Type ‘$:,~~equency (MHz)
ceramic+,,:,~f~ “
1.0
L s~~i~ ~ “
1.0
Temperature
Ooc
to
70°c
–40°C
to 85°C
Order Number
MC6800L
MC~~CL
Vccc
8
AC [ 9
Al [ 10
A2 [ 11
@y*+(k:::
Ti. .. ,
.
2.0
Ooc
to
70°c
~rdio
.—
! –!–
I
s suffix
Plastic
P
Suffix
1.0
1.0
1.5
1.5
2.0
1.0
1.0
1.5
1.5
2.0
O“c to 70°c
–40°C to 85°C
O“c to 70°c
–40°C to 85°C
O“c to 70°c
O“c to 70°c
–40°C
to
85°C
O“c
to
70°c
– 40°C
to
85°C
Ooc
to
70°c
MC68BOOL
MC68WS
MC@WCS
Mc68Ams
Mc68Amcs
MC68BOOS
MC6800P
MC6800C P
MC68AOOP
MC68AOOCP
MC68BOOP
A3[
A4[
12
13
A5 [ 14
A6 [ 15
A7 [ 16
A8 [ 17
A9 [ 16
A1O c
19
Al 1q 20
MOTOROLA INC., lW
DS9471-F
——
-——— -—
MAXIMUM
RATINGS
M C6~C
M C68A~C
Range
I
I
Tsta
I
-40to
+85
+150
I
I
Storage Temperature
l-55to
I “C I
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electrical fields; however, it is ad-
vised that normal precautions be taken to
avoid application of any voltage higher than
maximum-rated
voltages
to this high-
impedance circuit. Reliability of operation is
THERMAL
RESISTANCE
Rating
Symbol
eJ A
Value
Im
60
m
Unit
“Clw
Plastic Package
Cerdip Package
Ceramic Packaqe
POWER
The average
chip-junction
OJA)
temperature,
CONSIDERATIONS
from:
TJ, in ‘C can be obtained
TJ=TA+(PDo
Where:
TA = Ambient
OJA=
(1)
‘C
,.,\wy\
\ ~.::$,i~
;F’s~;
.,$ ‘f:?ki,,
, ,,$3
PD=PINT+PpORT
::i~.’. ~..,..,.
~i.:.,. .
.<,,..,,
PINT= ICC x Vcc, Watts – Chip Internal Power
1*+:
,..,
.,+*
PpORT = Port Power Dissipation, Watts – User Determin@:$,,,
..,.
. ,.,.
Package
Thermal
Resistance,
Junction-to-Ambient,
“C/W
Temperature,
For most applications PPORT< PINT and can be neglected. P$o~~
may become significant if the device is configured to
%i*\: ,, *F
,+,:,
*
drive Darlington bases or sink LED loads.
..,,,.,
,\+,*
An approximate relationship between PD and TJ (if PpO~~$YWbglected)
is:
,.>,,,.
PD= K- (TJ+2730C)
(2)
.,J:> ~,:*
,J,t::i,}
Solving equations 1 and 2 for K gives:
.,(*;{:\
K= PD. (TA+2730C)+0JA*
PD2
.. ‘}~. $
(3)
,’,:::
/:’\,.*:..*>.\\
Where K is a constant pertaining to the parti~$~$~~~it. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K the va~~~~:Qft,@Dand TJ can be obtained
\\*‘:*,..,,
value of TA,
,>f:?>,{,,,>i,
,t
~“,’.,,\<..
.~\ ‘~$,\ {w
.,!.
‘-.<~:,.
~~y
>
V’i, .\\
,::,2.CF
i?~jt:,?.
.
.},.
.
by solving equations(1)
and (2) iteratively for any
DC ELECTRICAL
CHARACTERl~%~C~(Vcc=
,..:$:,?,$ >
,,,..,,.,
5,0 Vdc, +5%,
Vss = O, TA= TL to TH unless otherwise noted)
Svmkl
Logic
41,42
Logic
~1 ,42
Logic
@l, #2
D&D7
AO-A15, Rlw
DO-D7
VMA
BA
VSS+2.4
VSS+2.4
VSS+2.41
VSS–0,3
VSS–0,3
1,0
VSS+O.8
VSS+O.4
2.5
v
“ .&i,t.
~~
\t$.<,%,\. @aracteriatic
“i’;,L,, ‘$,
,
Input High Voltage
,;>? “a?+$,}.,,’~
~.,t...t,
Input Low Voltage ~w”$&~$,$#
.,. , ‘<$
.,~’ \ .:,,
tat;.{,,,
*,,.;’.
Input Leakag@:$~&f$n~
(Vin =Ot&@&~~,
Vcc= Max)
V, Vcc=o V to
5.25 V)
(Vin
~&!0,~~@5
Hi-~@bkti@akage
Current
f~#’@&.4 to 2.4 V, Vcc = Max)
~w~?
High Voltage
A&A15,
R/~,
‘$$lLoad= -
205tiA, Vcc= MinJ
“(lLoad= – 1454A, VCC= Min)
(lLoad= – 100KA, VCC= Min)
Output Low Voltage (lLoad = 1.6 mA, VCC = Min)
Internal Power Dissipation
Capacitance
(Vin=O, TA=250C,
f=l.O
(Measured at TA = TL)
MHz)
PA
,
VOH
VOL
PINT
[
1,0
35
70
12.5
10
12
1
I
v
! —
I
I
I
]
I
Ivss+o
0.5
25
45
10
6.5
w
,4
v
w
I
I
I
I
~1
42
DGD7
Logic Inputs
AO-A15, Rl~,
VMA
Cin
pF
Cout
pF
(M)
MOTOROLA
Semjconducfor
2
Products Inc.
CLOCK TIMING (Vcc=
5,0
V,
*5%,
VSS=O,
Frequency of Operation
TA=TL
to TH unless otherwise
noted)
Symbol
Min
0.1
0.1
0.1
1.000
O.m
O.m
w
Za
180
90
600
w
o
o
Typ
Max
1.0
1.5
2.0
10
10
10
9m
9m
9W
Unit
MHz
Characteristic
MC~
MC68AO0
MCWBW
M Cm
M C@AW
MC~BW
@l, @2 – MCmN
@l, @2 – MC6BAO0
@l, @2 – MC68BO0
MCH
M C~A~
MC6BBW
f
Cycle Time (Figure 1)
tcyc
ps
Clock Pulse Width
(Measured at VCC– 0.6 V)
Total 01 and 42 Up Time
pW~H
ns
,*!.
‘*{,1,
.!>.,:..,.,.:
~:~,
Y “~:..
d *“:*’:*L
‘$$:fi+s:~
t“t
tr, tf ~
td
Rise and Fall Time (Measured between VSS +0.4 and VCC– O.6)
Delay Time or Clock Separation (Figure 1)
(Measured at VOV=VSS+O.6
V@tr=tf=l~
ns)
(Measured at VOV= VSS + 1.0 V@tr=tf S35 ns}
1,
,,,,
,,fj:$’,i~ ,’;?
,..~’
%$*t&
, ,,
>+1,:
–$; y< “$,
~
—.$:~,
?\:i..\*.’,
$
ns
td+
+
‘d+
. ,,
,,,.
b,’’”
<
vl~c*
,,
. ..>.,,,.
.~t~
4:.
- . $~~+’<.
~a..~+,k~
Character@i&$iF, ~~’
~\+,\ -i
*,. :
,~.;.,+ ‘:.$..
-. :$, ...
~’--
Address DelaV
..,,.
~,t~,,,:y
,
C=90pF
,,,,
**3::,:>
C=30 pF
,,..,
..
>
Peripheral Read Access ~fi&~f:
tacc = tut – (tAD +~~~$~.
Data Setup Tim$,:( ~~~?:
Input Data H@me
Output D~@ ‘~l,#Time
Addressf&,&,Jime
Ena~~i~@Time
Data ~lav
(Address, R/~,
for DBE Input
VMA)
*T,
,+1
Symbol
MC~
Min
605
lm
10
10
30
450
2m
o
Iw
Typ
25
50
Max
270
2W
225
Im
29
40
270
25
Min
m
60
10
10
30
280
140
0
120
MC8BAO0
Typ
25
a
Max
1BO
165
2W
100
165
40
270
25
Min
2W
40
10
10
m
220
110
0
75
MC6BBO0
Typ
25
50
Max
150
135
160
100
135
m
220
25
Unit
tA D
ns
tacc
tDSR
tH
tH
tA H
tEH
tDDW
tpcs
tpcr, tpcf
tBA
tTSE
tTSD
tDBE
tDBEr, tDBEf
ns
ns
ns
ns
ns
ns
ns
Time (Write)
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
8US Available DelaV
Hi-Z Enable
Hi-Z DelaV
Data Bus Enable Down Time During @l Up Time
Data Bus Enable Rise and Fall Times
ns
m
M070ROLA
Semiconductor
3
Products Inc.
1
FIGURE 2 – READ DATA FROM MEMORY OR PERIPHERALS
Start
of
/
@l
Cycle
+
‘VIHC
~
0.4 v
7
0.4 v
Data
Not
Valid
~
Start
of Cvcle
‘):.,
Data
From
MPU
2.4
V
[
0.4 v
I
ktDDw+
k\\\\\\Y
Data
Not
Valid
NOTES:
1.
Voltage levels shown are VLSO.4,
2. Measurement
VH> 2.4 V, unless otherwise
specified
noted
points shown are 0.8 V and 2.0 V, unless otherwise
MOTOROLA
@
Semiconductor
4
Produck
Inc.
FIGURE 4 – TYPICAL DATA BUS OUTPUT DELAY
versus
CAPACITIVE LOADING (TDDw)
600
‘lo
FIGURE 5 – TYPICAL READ/WRITE, VMA, AND ADDRESS
OUTPUT DELAY
versus
CAPACITIVE LOADING (TAD)
600
‘lo
500
I OH
=-205A
max @ 2.4 V
lo H=-145*max@2.4V
L=l.6mAmax@0.4v
L=l.6mAmax@0.4V
500 - Vcc = 5.0v
1A= 25°C
~
=
u
z
F
>
~
:
400
z
u
z
/
/
200
-
100
/
CL
includes stray capacitance
0’
0
100
200
CL,
LOAO
300
CAPACITANCE
-VCC=5.OV
TA =
25°C
-$
,:,
400
300
~
/
/
~
~
~
u
0
300
200
100
CL
includes stray capacitance
600
o
0
100
400
(pF)
500
2og~+~~
,i$oo
400
500
600
MOTOROLA
@
Semiconductor
5
Products Inc.
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