HC05RC17GRS/D
REV. 2.0
General Release Specification
CSIC MCU Design Center
Austin, Texas
N O N - D I S C L O S U R E
January 16, 1997
A G R E E M E N T
MC68HC05RC17
R E Q U I R E D
General Release Specifiation
R E Q U I R E D
A G R E E M E N T
N O N - D I S C L O S U R E
Motorola reserves the right to make changes without further notice to
any products herein to improve reliability, function or design. Motorola
does not assume any liability arising out of the application or use of any
product or circuit described herein; neither does it convey any license
under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended
to support or sustain life, or for any other application in which the failure
of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for
any such unintended or unauthorized application, Buyer shall indemnify
and hold Motorola and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or
indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
General Release Specification
2
MC68HC05RC17
—
Rev. 2.0
MOTOROLA
General Release Specification — MC68HC05RC17
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 15
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 33
Section 4, Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . . . . 55
Section 7. Parallel Input/Output (I/O) . . . . . . . . . . . . . . 59
Section 8. Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 9. Carrier Modulator Transmitter (CMT) . . . . . . 69
Section 10. Phase-Locked Loop (PLL) Synthesizer . . . . 87
Section 11. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . 93
Section 12. Electrical Specifications . . . . . . . . . . . . . . 111
Section 13. Mechanical Specifications . . . . . . . . . . . 121
Section 14. Ordering Information . . . . . . . . . . . . . . . . 123
MC68HC05RC17
—
Rev. 2.0
MOTOROLA
List of Sections
General Release Specification
3
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
List of Sections
R E Q U I R E D
N O N - D I S C L O S U R E
General Release Specification
4
List of Sections
A G R E E M E N T
MC68HC05RC17
—
Rev. 2.0
MOTOROLA
General Release Specification — MC68HC05RC17
Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Section 2. Memory
2.1
2.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3.1
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.2
ROM Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3.3
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
MC68HC05RC17
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Rev. 2.0
MOTOROLA
Table of Contents
General Release Specification
5
N O N - D I S C L O S U R E
1.5
Signal Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.1
V
DD
and V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.2
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .22
1.5.3
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.5.4
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.5
LPRST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5.6
IRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.7
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.8
Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.5.9
Port C (PC0–PC1 and PC4–PC7). . . . . . . . . . . . . . . . . . . .24
1.5.10
XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.11
V
DDSYN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
A G R E E M E N T
R E Q U I R E D
