Freescale Semiconductor, Inc.
Addendum
HC908JB8AD/D
Rev. 0, 4/2002
Addendum to
MC68HC908JB8
Technical Data
Freescale Semiconductor, Inc...
This addendum provides additional information to the
MC68HC908JB8 Technical Data,
Rev. 2
(Motorola document number MC68HC908JB8/D),
MC68HC08JB8A
The MC68HC08JB8A is the ROM part equivalent to the MC68HC908JB8. The
entire MC68HC908JB8 data book apply to this ROM device, with exceptions
outlined in this addendum.
Table 1. Summary of MC68HC08JB8A and MC68HC908JB8 Differences
MC68HC08JB8A
Memory ($DC00–$FBFF)
User vectors ($FFF0–$FFFF)
Registers at $FE08 and $FF09
8,192 bytes ROM
16 bytes ROM
Not used;
locations are reserved.
$FC00–$FDFF: Not used.
$FE10–$FFDF: Used for
testing purposes only.
V
DD
level (5V logic)
MC68HC908JB8
8,192 bytes FLASH
16 bytes FLASH
FLASH related registers.
$FE08 — FLCR
$FF09 — FLBPR
Used for testing and FLASH
programming/erasing.
V
REG
level (3.3V logic)
Monitor ROM
($FC00–$FDFF and $FE10–$FFDF)
OSC1 and OSC2 pins
MCU Block Diagram
Figure 1
shows the block diagram of the MC68HC08JB8A.
Memory Map
The MC68HC08JB8A has 8,192 bytes of user ROM from $DC00 to $FBFF, and
16 bytes of user ROM vectors from $FFF0 to $FFFF. On the MC68HC908JB8,
these memory locations are FLASH memory.
Figure 2
shows the memory map of the MC68HC08JB8A.
© Motorola, Inc., 2003
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INTERNAL BUS
PTA7/KBA7
(3)
PTA
:
PTA0/KBA0
(3)
DDRA
KEYBOARD INTERRUPT
MODULE
DDRB
PTB
PTB7–PTB0
(3)
HC908JB8AD/D
MONITOR ROM — 464 BYTES
LOW VOLTAGE INHIBIT
MODULE
DDRD
PTD
USER ROM VECTORS — 16 BYTES
DDRC
PTC
(1), (3)
DDRE
PTE
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POWER-ON RESET
MODULE
COMPUTER OPERATING PROPERLY
MODULE
USB
MODULE
USB ENDPOINT 0, 1, 2
(1) Pins have 5V logic.
(2) Pins have integrated pullup device.
(3) Pins have software configurable pull-up device.
(4) Pins are open-drain when configured as output.
(5) Pins have 10mA sink capability.
(6) Pins have 25mA sink capability.
Shaded blocks indicate differences to MC68HC908JB8
V
SS
V
REG
(3.3 V)
INTERNAL VOLTAGE REGULATOR
MOTOROLA
Figure 1. MC68HC08JB8A Block Diagram
LS USB
TRANSCEIVER
2
TIMER INTERFACE
MODULE
BREAK
MODULE
PTC7–PTC0
(3)
PTD7–PTD6
(4)
PTD5–PTD2
(4) (5)
PTD1–PTD0
(4) (6)
PTE4/D–
(3) (4) (5)
PTE3/D+
(3) (4) (5)
PTE2/TCH1
(3)
PTE1/TCH0
(3)
PTE0/TCLK
(3)
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
CONTROL AND STATUS REGISTERS — 64 BYTES
USER ROM — 8,192 BYTES
USER RAM — 256 BYTES
(1)
OSC1
(1)
OSC2
OSCILLATOR
(1), (2)
RST
SYSTEM INTEGRATION
MODULE
IRQ
IRQ
MODULE
V
DD
Addendum to MC68HC908JB8 Technical Data
POWER
Freescale Semiconductor, Inc.
HC908JB8AD/D
MC68HC08JB8A
$0000
↓
$003F
$0040
↓
$013F
$0140
↓
$DBFF
$DC00
↓
$FBFF
$FC00
↓
$FDFF
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
$FE0D
$FE0E
$FE0F
$FE10
↓
$FFDF
$FFE0
↓
$FFEF
$FFF0
↓
$FFFF
I/O Registers
64 Bytes
RAM
256 Bytes
Unimplemented
56,000 Bytes
ROM
8,192 Bytes
Unimplemented
512 Bytes
Break Status Register (BSR)
Reset Status Register (RSR)
Reserved
Break Flag Control Register (BFCR)
Interrupt Status Register 1 (INT1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Break Address High Register (BRKH)
Break Address Low Register (BRKL)
Break Status and Control Register (BRKSCR)
Reserved
Monitor ROM
464 Bytes
Reserved
16 Bytes
ROM Vectors
16 Bytes
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Figure 2. MC68HC08JB8A Memory Map
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Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the
MC68HC08JB8A.
On the MC68HC908JB8, these two locations are the FLASH control register
and the FLASH block protect register respectively.
Monitor ROM
The monitor program (monitor ROM: $FE10–$FFDF) on the MC68HC08JB8A
is for device testing only. $FC00–$FDFF are unused.
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Electrical
Specifications
DC Electrical
Characteristics
Electrical specifications for the MC68HC908JB8 apply to the MC68HC08JB8A,
except for the parameters indicated below.
Table 2. DC Electrical Characteristics
Characteristic
(1)
Regulator output voltage
Output high voltage (I
Load
= –2.0 mA)
PTA0–PTA7, PTB0–PTB7, PTC0–PTC7,
PTE0–PTE2
Output low voltage
(I
Load
= 1.6 mA) All I/O pins
(I
Load
= 25 mA) PTD0–PTD1 in ILDD mode
(I
Load
= 10 mA) PTE3–PTE4 with USB disabled
Input high voltage
All ports, OSC1
IRQ, RST
Input low voltage
All ports, OSC1
IRQ, RST
Output low current (V
OL
= 2.0 V)
PTD2–PTD5 in LDD mode
V
DD
supply current, V
DD
= 5.25V, f
OP
= 3MHz
Run, with low speed USB
(3)
Run, with USB suspended
(3)
Wait, with low speed USB
(4)
Wait, with USB suspended
(4)
Stop
(5)
0
°
C to 70
°
C
—
—
—
—
—
6.0 (5.0)
5.5 (4.5)
4.0 (3.0)
3.0 (2.5)
30
7.5
6.5
5.0
4.0
100
mA
mA
mA
mA
Symbol
V
REG
V
OH
Min
3.0
V
REG
–0.8
Typ
(2)
3.3
—
Max
3.6
—
Unit
V
V
V
OL
—
—
—
0.7
×
V
REG
0.7
×
V
DD
V
SS
V
SS
12 (17)
—
—
—
—
—
—
—
17 (22)
0.4
0.5
0.4
V
REG
V
DD
0.3
×
V
REG
0.3
×
V
DD
22 (27)
V
V
IH
V
V
IL
V
I
OL
mA
I
DD
µ
A
4
Addendum to MC68HC908JB8 Technical Data
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HC908JB8AD/D
MC68HC08JB8A
Table 2. DC Electrical Characteristics
Characteristic
(1)
I/O ports Hi-Z leakage current
Input current
Capacitance
Ports (as input or output)
POR re-arm voltage
(6)
POR rise-time ramp rate
(7)
Symbol
I
IL
I
IN
C
Out
C
In
V
POR
R
POR
V
DD
+
V
HI
R
PU
Min
—
—
—
—
0
0.035
1.4
×
V
DD
25
4
1.2
2.8 (2.4)
40
5
1.5
3.3 (2.7)
Typ
(2)
—
—
—
—
—
—
Max
Unit
±
10
±
1
12
8
100
—
2
×
V
DD
55
6
2.0
3.8 (3.0)
(8)
µ
A
µ
A
pF
mV
V/ms
V
k
Ω
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Monitor mode entry voltage
Pullup resistors
Port A, port B, port C, PTE0–PTE2, RST, IRQ
PTE3–PTE4 (with USB module disabled)
D– (with USB module enabled)
LVI reset
V
LVR
V
1. V
DD
= 4.0 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°C
only.
3. Run (operating) I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I
DD
. Measured with all modules enabled.
4. Wait I
DD
measured using external square wave clock source (f
XCLK
= 6 MHz); all inputs 0.2 V from rail; no dc loads; less
than 100 pF on all outputs. C
L
= 20 pF on OSC2; 15 kΩ
±
5% termination resistors on D+ and D– pins; all ports configured
as inputs; OSC2 capacitance linearly affects wait I
DD
5. STOP I
DD
measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 kΩ
±
5% between V
REG
and D– pins and 15 kΩ
±
5% termination resistor on D+ pin; no port pins sourcing current.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V
REG
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
REG
is reached.
8. The numbers in parenthesis are MC68HC08JB8 (non-A part) values.
Memory
Characteristics
Table 3. Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
V
RDR
Min
1.3
Max
—
Unit
V
Notes:
Since MC68HC08JB8A is a ROM device, FLASH memory electrical characteristics do not apply.
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Addendum to MC68HC908JB8 Technical Data
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